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arm: zynq: Add support for system reset 

Do system reset via slcr registers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2013-03-20 11:42:15 +01:00
parent 64b889b39e
commit 96790f0a28
3 changed files with 34 additions and 0 deletions
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6
arch/arm/mach-zynq/common.c
View File

@ -92,6 +92,11 @@ static void __init xilinx_map_io(void)
zynq_scu_map_io();
}
static void zynq_system_reset(char mode, const char *cmd)
{
zynq_slcr_system_reset();
}
static const char *xilinx_dt_match[] = {
"xlnx,zynq-zc702",
"xlnx,zynq-7000",
@ -104,4 +109,5 @@ MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
.init_machine = xilinx_init_machine,
.init_time = xilinx_zynq_timer_init,
.dt_compat = xilinx_dt_match,
.restart = zynq_system_reset,
MACHINE_END

1
arch/arm/mach-zynq/common.h
View File

@ -18,6 +18,7 @@
#define __MACH_ZYNQ_COMMON_H__
extern int zynq_slcr_init(void);
extern void zynq_slcr_system_reset(void);
extern void __iomem *zynq_slcr_base;
extern void __iomem *zynq_scu_base;

27
arch/arm/mach-zynq/slcr.c
View File

@ -32,8 +32,35 @@
#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_UNLOCK 0x8 /* SCLR unlock register */
#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
void __iomem *zynq_slcr_base;
/**
* zynq_slcr_system_reset - Reset the entire system.
*/
void zynq_slcr_system_reset(void)
{
u32 reboot;
/*
* Unlock the SLCR then reset the system.
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK);
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS);
writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS);
writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
}
/**
* zynq_slcr_init
* Returns 0 on success, negative errno otherwise.