mirror of https://gitee.com/openkylin/linux.git
ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108
Rockchip finally named the SOC as RV1108, so change it for compatible. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [adapt include in rk1108-evb.dts to not introduce errors] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -40,7 +40,7 @@
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/dts-v1/;
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#include "rk1108.dtsi"
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#include "rv1108.dtsi"
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/ {
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model = "Rockchip RK1108 Evaluation board";
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@ -47,7 +47,7 @@ / {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rk1108";
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compatible = "rockchip,rv1108";
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interrupt-parent = <&gic>;
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@ -113,7 +113,7 @@ bus_intmem@10080000 {
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};
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uart2: serial@10210000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10210000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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@ -127,7 +127,7 @@ uart2: serial@10210000 {
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};
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uart1: serial@10220000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10220000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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@ -141,7 +141,7 @@ uart1: serial@10220000 {
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};
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uart0: serial@10230000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10230000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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@ -155,17 +155,17 @@ uart0: serial@10230000 {
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};
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grf: syscon@10300000 {
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compatible = "rockchip,rk1108-grf", "syscon";
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compatible = "rockchip,rv1108-grf", "syscon";
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reg = <0x10300000 0x1000>;
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};
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pmugrf: syscon@20060000 {
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compatible = "rockchip,rk1108-pmugrf", "syscon";
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compatible = "rockchip,rv1108-pmugrf", "syscon";
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reg = <0x20060000 0x1000>;
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};
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cru: clock-controller@20200000 {
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compatible = "rockchip,rk1108-cru";
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compatible = "rockchip,rv1108-cru";
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reg = <0x20200000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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@ -173,7 +173,7 @@ cru: clock-controller@20200000 {
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};
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emmc: dwmmc@30110000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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@ -185,7 +185,7 @@ emmc: dwmmc@30110000 {
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};
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sdio: dwmmc@30120000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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@ -197,7 +197,7 @@ sdio: dwmmc@30120000 {
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};
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sdmmc: dwmmc@30130000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 100000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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