mirror of https://gitee.com/openkylin/linux.git
ARM: OMAP4: PM: OMAP4 clock tree and clkdev registration
This patch defines all the clock nodes in OMAP4430 platform. All the clock node structs and the clkdev table is autogenerated using a python script (gen_clock_tree.py) developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
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@ -0,0 +1,23 @@
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/*
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* OMAP4 clock function prototypes and macros
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
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unsigned long omap3_dpll_recalc(struct clk *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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/* DPLL modes */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOCKED 0x7
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#define OMAP4430_MAX_DPLL_MULT 2048
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#define OMAP4430_MAX_DPLL_DIV 128
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extern const struct clkops clkops_noncore_dpll_ops;
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#endif
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@ -35,7 +35,7 @@ struct omap_clk {
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#define CK_343X (1 << 6)
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#define CK_3430ES1 (1 << 7)
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#define CK_3430ES2 (1 << 8)
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#define CK_443X (1 << 9)
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#endif
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@ -150,6 +150,8 @@ extern const struct clkops clkops_null;
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#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
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#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
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#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
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#define CLOCK_IN_OMAP4430 (1 << 13)
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#define ALWAYS_ENABLED (1 << 14)
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/* bits 13-31 are currently free */
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/* Clksel_rate flags */
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@ -158,6 +160,7 @@ extern const struct clkops clkops_null;
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#define RATE_IN_243X (1 << 2)
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#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
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#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
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#define RATE_IN_4430 (1 << 5)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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