mirror of https://gitee.com/openkylin/linux.git
drm/i915/dp: abstract dp link config computation from the rest
Abstract a new intel_dp_compute_link_config() from intel_dp_compute_config(), with the parts related to link configuration, i.e. bpp, link rate, and lane count selection. No functional changes. v2: Fix a checkpatch warn about spacing. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/80f99a625633f87f44d38d487ba3b32ff9a26b07.1524730974.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
dd519418f5
commit
981a63eb27
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@ -1685,19 +1685,14 @@ static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
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return bres;
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}
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bool
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intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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static bool
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intel_dp_compute_link_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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enum port port = encoder->port;
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struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(conn_state);
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int lane_count, clock;
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int min_lane_count = 1;
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int max_lane_count = intel_dp_max_lane_count(intel_dp);
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@ -1706,9 +1701,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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int bpp, mode_rate;
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int link_avail, link_clock;
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int common_len;
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bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
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DP_DPCD_QUIRK_LIMITED_M_N);
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common_len = intel_dp_common_len_rate_limit(intel_dp,
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intel_dp->max_link_rate);
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@ -1717,51 +1709,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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max_clock = common_len - 1;
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if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
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pipe_config->has_pch_encoder = true;
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pipe_config->has_drrs = false;
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if (IS_G4X(dev_priv) || port == PORT_A)
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pipe_config->has_audio = false;
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else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
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pipe_config->has_audio = intel_dp->has_audio;
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else
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pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
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if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
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struct drm_display_mode *panel_mode =
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intel_connector->panel.alt_fixed_mode;
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struct drm_display_mode *req_mode = &pipe_config->base.mode;
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if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
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panel_mode = intel_connector->panel.fixed_mode;
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drm_mode_debug_printmodeline(panel_mode);
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intel_fixed_panel_mode(panel_mode, adjusted_mode);
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if (INTEL_GEN(dev_priv) >= 9) {
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int ret;
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ret = skl_update_scaler_crtc(pipe_config);
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if (ret)
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return ret;
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}
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if (HAS_GMCH_DISPLAY(dev_priv))
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intel_gmch_panel_fitting(intel_crtc, pipe_config,
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conn_state->scaling_mode);
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else
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intel_pch_panel_fitting(intel_crtc, pipe_config,
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conn_state->scaling_mode);
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}
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if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return false;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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return false;
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/* Use values requested by Compliance Test Request */
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if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
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int index;
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@ -1831,23 +1778,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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return false;
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found:
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if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
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/*
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* See:
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* CEA-861-E - 5.1 Default Encoding Parameters
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* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
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*/
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pipe_config->limited_color_range =
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bpp != 18 &&
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drm_default_rgb_quant_range(adjusted_mode) ==
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HDMI_QUANTIZATION_RANGE_LIMITED;
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} else {
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pipe_config->limited_color_range =
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intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
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}
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pipe_config->lane_count = lane_count;
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pipe_config->pipe_bpp = bpp;
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pipe_config->port_clock = intel_dp->common_rates[clock];
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@ -1856,7 +1787,90 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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DRM_DEBUG_KMS("DP link bw required %i available %i\n",
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mode_rate, link_avail);
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intel_link_compute_m_n(bpp, lane_count,
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return true;
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}
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bool
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intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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enum port port = encoder->port;
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struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(conn_state);
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bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
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DP_DPCD_QUIRK_LIMITED_M_N);
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if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
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pipe_config->has_pch_encoder = true;
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pipe_config->has_drrs = false;
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if (IS_G4X(dev_priv) || port == PORT_A)
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pipe_config->has_audio = false;
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else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
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pipe_config->has_audio = intel_dp->has_audio;
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else
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pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
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if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
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struct drm_display_mode *panel_mode =
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intel_connector->panel.alt_fixed_mode;
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struct drm_display_mode *req_mode = &pipe_config->base.mode;
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if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
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panel_mode = intel_connector->panel.fixed_mode;
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drm_mode_debug_printmodeline(panel_mode);
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intel_fixed_panel_mode(panel_mode, adjusted_mode);
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if (INTEL_GEN(dev_priv) >= 9) {
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int ret;
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ret = skl_update_scaler_crtc(pipe_config);
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if (ret)
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return ret;
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}
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if (HAS_GMCH_DISPLAY(dev_priv))
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intel_gmch_panel_fitting(intel_crtc, pipe_config,
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conn_state->scaling_mode);
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else
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intel_pch_panel_fitting(intel_crtc, pipe_config,
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conn_state->scaling_mode);
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}
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if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return false;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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return false;
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if (!intel_dp_compute_link_config(encoder, pipe_config))
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return false;
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if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
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/*
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* See:
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* CEA-861-E - 5.1 Default Encoding Parameters
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* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
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*/
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pipe_config->limited_color_range =
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pipe_config->pipe_bpp != 18 &&
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drm_default_rgb_quant_range(adjusted_mode) ==
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HDMI_QUANTIZATION_RANGE_LIMITED;
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} else {
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pipe_config->limited_color_range =
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intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
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}
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intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
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adjusted_mode->crtc_clock,
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pipe_config->port_clock,
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&pipe_config->dp_m_n,
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@ -1865,11 +1879,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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if (intel_connector->panel.downclock_mode != NULL &&
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dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
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pipe_config->has_drrs = true;
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intel_link_compute_m_n(bpp, lane_count,
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intel_connector->panel.downclock_mode->clock,
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pipe_config->port_clock,
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&pipe_config->dp_m2_n2,
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reduce_m_n);
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intel_link_compute_m_n(pipe_config->pipe_bpp,
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pipe_config->lane_count,
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intel_connector->panel.downclock_mode->clock,
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pipe_config->port_clock,
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&pipe_config->dp_m2_n2,
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reduce_m_n);
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}
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/*
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