From a36deff6d13da8e146ad02cf38c0b81752efb305 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:53 +0800 Subject: [PATCH 01/12] PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init() We called dw_pcie_setup_rc() from the ls1021a host init function, but not from the common ls_pcie_host_init() function, so platforms other than ls1021a still depended on initialization by the bootloader. Call dw_pcie_setup_rc() from ls_pcie_host_init() to reduce dependencies on the bootloader. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 7581490f007c..aebefb42377a 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -165,6 +165,8 @@ static int ls_pcie_host_init(struct pcie_port *pp) ls_pcie_drop_msg_tlp(pcie); iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + dw_pcie_setup_rc(pp); + return 0; } From 02232343349e606c8809e2555985a806d615e4ee Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:54 +0800 Subject: [PATCH 02/12] PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket The STRFMR1 is not a DBI read-only register, so move it out from the write-enable bracket. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index aebefb42377a..c16940044ed6 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -162,9 +162,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); - ls_pcie_drop_msg_tlp(pcie); iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + ls_pcie_drop_msg_tlp(pcie); + dw_pcie_setup_rc(pp); return 0; From 5da39bf0919b6e129010f1554e639940be5bcdce Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:55 +0800 Subject: [PATCH 03/12] PCI: layerscape: Add class code and multifunction fixups for ls1021a The current code depends on class code and multifunction fixups done by the bootloader. Perform these fixups in ls1021_pcie_host_init() to remove this dependency. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index c16940044ed6..3aa34214643c 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -134,6 +134,11 @@ static int ls1021_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); + iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + ls_pcie_drop_msg_tlp(pcie); return 0; From ba95a82e31490b2415e9fe967c6997f5dac8fe31 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:56 +0800 Subject: [PATCH 04/12] PCI: layerscape: Move generic init functions earlier in file We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from device-specific routines. Move the generic functions earlier in the file so we won't need forward declarations. This is strictly a code move with no functional change intended. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 64 ++++++++++++++++---------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 3aa34214643c..160035efa4d9 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -108,6 +108,38 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci) return 1; } +static int ls_pcie_link_up(struct dw_pcie *pci) +{ + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 state; + + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> + pcie->drvdata->ltssm_shift) & + LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; + + return 1; +} + +static int ls_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + + ls_pcie_drop_msg_tlp(pcie); + + dw_pcie_setup_rc(pp); + + return 0; +} + static int ls1021_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -144,38 +176,6 @@ static int ls1021_pcie_host_init(struct pcie_port *pp) return 0; } -static int ls_pcie_link_up(struct dw_pcie *pci) -{ - struct ls_pcie *pcie = to_ls_pcie(pci); - u32 state; - - state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> - pcie->drvdata->ltssm_shift) & - LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; - - return 1; -} - -static int ls_pcie_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct ls_pcie *pcie = to_ls_pcie(pci); - - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); - ls_pcie_fix_class(pcie); - ls_pcie_clear_multifunction(pcie); - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); - - ls_pcie_drop_msg_tlp(pcie); - - dw_pcie_setup_rc(pp); - - return 0; -} - static int ls_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip) { From fa92dba92c0026a8378085dbeab8a1d8ad8476c6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:57 +0800 Subject: [PATCH 05/12] PCI: layerscape: Refactor ls1021_pcie_host_init() ls1021_pcie_host_init() duplicated the code in the generic ls_pcie_host_init(). Call ls_pcie_host_init() instead of duplicating the code. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 160035efa4d9..27234dae4cba 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -164,16 +164,7 @@ static int ls1021_pcie_host_init(struct pcie_port *pp) } pcie->index = index[1]; - dw_pcie_setup_rc(pp); - - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); - ls_pcie_fix_class(pcie); - ls_pcie_clear_multifunction(pcie); - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); - - ls_pcie_drop_msg_tlp(pcie); - - return 0; + return ls_pcie_host_init(pp); } static int ls_pcie_msi_host_init(struct pcie_port *pp, From 4a2745d760facac895c107bed41e167e3806fced Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:58 +0800 Subject: [PATCH 06/12] PCI: layerscape: Disable outbound windows configured by bootloader Disable all the outbound windows to avoid one transaction hitting multiple outbound windows. dw_pcie_setup_rc() will reconfigure the outbound windows, which may conflict with windows configured by the bootloader. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 27234dae4cba..a77f7562c310 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -35,6 +35,8 @@ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ +#define PCIE_IATU_NUM 6 + struct ls_pcie_drvdata { u32 lut_offset; u32 ltssm_shift; @@ -91,6 +93,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) iowrite32(val, pci->dbi_base + PCIE_STRFMR1); } +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) +{ + int i; + + for (i = 0; i < PCIE_IATU_NUM; i++) + dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i); +} + static int ls1021_pcie_link_up(struct dw_pcie *pci) { u32 state; @@ -128,6 +138,13 @@ static int ls_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); + /* + * Disable outbound windows configured by the bootloader to avoid + * one transaction hitting multiple outbound windows. + * dw_pcie_setup_rc() will reconfigure the outbound windows. + */ + ls_pcie_disable_outbound_atus(pcie); + iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); From e44abfed6fcb750d24f4438dc9d5a02eebb5fcac Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:52:59 +0800 Subject: [PATCH 07/12] PCI: dwc: Add accessors for write permission of DBI read-only registers The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Joao Pinto Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 5 ++--- drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index a77f7562c310..627e2ed48090 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -33,7 +33,6 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ #define PCIE_IATU_NUM 6 @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) */ ls_pcie_disable_outbound_atus(pcie); - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); + dw_pcie_dbi_ro_wr_en(pci); ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + dw_pcie_dbi_ro_wr_dis(pci); ls_pcie_drop_msg_tlp(pcie); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index 7366c8167404..0c5f874345f6 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -76,6 +76,9 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define PCIE_DBI_RO_WR_EN (0x1 << 0) + /* * iATU Unroll-specific register definitions * From 4.80 core version the address translation will be made by unroll @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); } +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val |= PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) +{ + u32 reg; + u32 val; + + reg = PCIE_MISC_CONTROL_1_OFF; + val = dw_pcie_readl_dbi(pci, reg); + val &= ~PCIE_DBI_RO_WR_EN; + dw_pcie_writel_dbi(pci, reg, val); +} + #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); From d91dfe5054d4f2c424bd70ca34fc3328ee179f20 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:53:00 +0800 Subject: [PATCH 08/12] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt Pin registers, but the fixes don't actually work because these registers are read-only. Enable write permission before updating the Class Code and Interrupt Pin. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Joao Pinto Acked-by: Roy Zang --- drivers/pci/dwc/pcie-designware-host.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 99cb70b5de79..0985aeee917c 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -597,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); /* setup interrupt pins */ + dw_pcie_dbi_ro_wr_en(pci); val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_dbi_ro_wr_dis(pci); /* setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); @@ -637,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + /* Enable write permission for the DBI read-only register */ + dw_pcie_dbi_ro_wr_en(pci); /* program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + /* Better disable write permission right after the update */ + dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; From c3f909398827b03fad9391951b3daa4a11dcf663 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:53:01 +0800 Subject: [PATCH 09/12] PCI: layerscape: Remove unnecessary class code fixup Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup from the Layerscape driver. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pci-layerscape.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 627e2ed48090..3f53826b127e 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); } -/* Fix class value */ -static void ls_pcie_fix_class(struct ls_pcie *pcie) -{ - struct dw_pcie *pci = pcie->pci; - - iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE); -} - /* Drop MSG TLP except for Vendor MSG */ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) { @@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp) ls_pcie_disable_outbound_atus(pcie); dw_pcie_dbi_ro_wr_en(pci); - ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); dw_pcie_dbi_ro_wr_dis(pci); From b015b37e6693de515982452eebd6a9d19201f0fe Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 28 Aug 2017 18:53:01 +0800 Subject: [PATCH 10/12] PCI: artpec6: Stop enabling writes to DBI read-only registers Previously we enabled writes to the DBI read-only registers so the Class Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc() enables write permission itself, so we don't need to do it here. Stop enabling writes to the DBI read-only registers. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Roy Zang --- drivers/pci/dwc/pcie-artpec6.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index 5d81f1d884e3..d153491f600f 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); usleep_range(100, 200); - /* - * Enable writing to config regs. This is required as the Synopsys - * driver changes the class code. That register needs DBI write enable. - */ - dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); - /* setup root complex */ dw_pcie_setup_rc(pp); From 8f89357094e67bb09456457a00bbad4002293d15 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 4 Aug 2017 14:41:33 +0800 Subject: [PATCH 11/12] PCI: layerscape: Add support for ls2088a The ls2088a PCIe controller's register addresses are different from ls2080a, so add a match entry to identify ls2088a PCIe. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Minghuan Lian --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + drivers/pci/dwc/pci-layerscape.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ee1c72d5162e..2057b0000c72 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -15,6 +15,7 @@ Required properties: - compatible: should contain the platform identifier such as: "fsl,ls1021a-pcie", "snps,dw-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls2088a-pcie" "fsl,ls1046a-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 3f53826b127e..780eab9beb1e 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -244,12 +244,21 @@ static struct ls_pcie_drvdata ls2080_drvdata = { .dw_pcie_ops = &dw_ls_pcie_ops, }; +static struct ls_pcie_drvdata ls2088_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 0, + .lut_dbg = 0x407fc, + .ops = &ls_pcie_host_ops, + .dw_pcie_ops = &dw_ls_pcie_ops, +}; + static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata }, { }, }; From 03fc6134c260930b3784fd0a06edcf44f4e39581 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 4 Aug 2017 14:41:34 +0800 Subject: [PATCH 12/12] PCI: layerscape: Add support for ls1088a Add support for ls1088a. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Minghuan Lian --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + drivers/pci/dwc/pci-layerscape.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 2057b0000c72..ebf3feffed8a 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -16,6 +16,7 @@ Required properties: "fsl,ls1021a-pcie", "snps,dw-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" "fsl,ls2088a-pcie" + "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 780eab9beb1e..87fa486bee2c 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -259,6 +259,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata }, { }, };