mirror of https://gitee.com/openkylin/linux.git
perf_counter: powerpc: Make powerpc perf_counter code safe for 32-bit kernels
This abstracts a few things in arch/powerpc/kernel/perf_counter.c that are specific to 64-bit kernels, and provides definitions for 32-bit kernels. In particular, * Only 64-bit has MMCRA and the bits in it that give information about a PMU interrupt (sampled PR, HV, slot number etc.) * Only 64-bit has the lppaca and the lppaca->pmcregs_in_use field * Use of SDAR is confined to 64-bit for now * Only 64-bit has soft/lazy interrupt disable and therefore pseudo-NMIs (interrupts that occur while interrupts are soft-disabled) * Only 64-bit has PMC7 and PMC8 * Only 64-bit has the MSR_HV bit. This also fixes the types used in a couple of places, where we were using long types for things that need to be 64-bit. Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: linuxppc-dev@ozlabs.org Cc: benh@kernel.crashing.org LKML-Reference: <19000.55590.634126.876084@cargo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paul Mackerras
Ingo Molnar
parent
079b3c569c
commit
98fb1807b9
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@ -46,6 +46,115 @@ struct power_pmu *ppmu;
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*/
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static unsigned int freeze_counters_kernel = MMCR0_FCS;
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/*
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* 32-bit doesn't have MMCRA but does have an MMCR2,
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* and a few other names are different.
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*/
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#ifdef CONFIG_PPC32
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#define MMCR0_FCHV 0
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#define MMCR0_PMCjCE MMCR0_PMCnCE
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#define SPRN_MMCRA SPRN_MMCR2
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#define MMCRA_SAMPLE_ENABLE 0
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static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
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{
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return 0;
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}
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static inline void perf_set_pmu_inuse(int inuse) { }
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static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
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static inline u32 perf_get_misc_flags(struct pt_regs *regs)
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{
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return 0;
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}
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static inline void perf_read_regs(struct pt_regs *regs) { }
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static inline int perf_intr_is_nmi(struct pt_regs *regs)
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{
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return 0;
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}
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#endif /* CONFIG_PPC32 */
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/*
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* Things that are specific to 64-bit implementations.
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*/
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#ifdef CONFIG_PPC64
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static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
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{
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unsigned long mmcra = regs->dsisr;
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if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
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unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
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if (slot > 1)
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return 4 * (slot - 1);
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}
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return 0;
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}
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static inline void perf_set_pmu_inuse(int inuse)
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{
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get_lppaca()->pmcregs_in_use = inuse;
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}
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/*
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* The user wants a data address recorded.
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* If we're not doing instruction sampling, give them the SDAR
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* (sampled data address). If we are doing instruction sampling, then
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* only give them the SDAR if it corresponds to the instruction
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* pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
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* bit in MMCRA.
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*/
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static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
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{
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unsigned long mmcra = regs->dsisr;
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unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
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POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
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if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
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*addrp = mfspr(SPRN_SDAR);
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}
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static inline u32 perf_get_misc_flags(struct pt_regs *regs)
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{
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unsigned long mmcra = regs->dsisr;
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if (TRAP(regs) != 0xf00)
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return 0; /* not a PMU interrupt */
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if (ppmu->flags & PPMU_ALT_SIPR) {
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if (mmcra & POWER6_MMCRA_SIHV)
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return PERF_EVENT_MISC_HYPERVISOR;
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return (mmcra & POWER6_MMCRA_SIPR) ?
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PERF_EVENT_MISC_USER : PERF_EVENT_MISC_KERNEL;
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}
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if (mmcra & MMCRA_SIHV)
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return PERF_EVENT_MISC_HYPERVISOR;
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return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
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PERF_EVENT_MISC_KERNEL;
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}
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/*
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* Overload regs->dsisr to store MMCRA so we only need to read it once
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* on each interrupt.
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*/
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static inline void perf_read_regs(struct pt_regs *regs)
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{
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regs->dsisr = mfspr(SPRN_MMCRA);
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}
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/*
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* If interrupts were soft-disabled when a PMU interrupt occurs, treat
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* it as an NMI.
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*/
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static inline int perf_intr_is_nmi(struct pt_regs *regs)
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{
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return !regs->softe;
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}
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#endif /* CONFIG_PPC64 */
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static void perf_counter_interrupt(struct pt_regs *regs);
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void perf_counter_print_debug(void)
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@ -78,12 +187,14 @@ static unsigned long read_pmc(int idx)
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case 6:
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val = mfspr(SPRN_PMC6);
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break;
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#ifdef CONFIG_PPC64
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case 7:
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val = mfspr(SPRN_PMC7);
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break;
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case 8:
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val = mfspr(SPRN_PMC8);
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break;
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#endif /* CONFIG_PPC64 */
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default:
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printk(KERN_ERR "oops trying to read PMC%d\n", idx);
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val = 0;
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@ -115,12 +226,14 @@ static void write_pmc(int idx, unsigned long val)
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case 6:
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mtspr(SPRN_PMC6, val);
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break;
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#ifdef CONFIG_PPC64
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case 7:
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mtspr(SPRN_PMC7, val);
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break;
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case 8:
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mtspr(SPRN_PMC8, val);
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break;
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#endif /* CONFIG_PPC64 */
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default:
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printk(KERN_ERR "oops trying to write PMC%d\n", idx);
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}
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@ -283,7 +396,7 @@ static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
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static void power_pmu_read(struct perf_counter *counter)
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{
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long val, delta, prev;
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s64 val, delta, prev;
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if (!counter->hw.idx)
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return;
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@ -477,7 +590,7 @@ void hw_perf_enable(void)
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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if (cpuhw->n_counters == 0)
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get_lppaca()->pmcregs_in_use = 0;
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perf_set_pmu_inuse(0);
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goto out_enable;
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}
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@ -510,7 +623,7 @@ void hw_perf_enable(void)
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* bit set and set the hardware counters to their initial values.
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* Then unfreeze the counters.
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*/
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get_lppaca()->pmcregs_in_use = 1;
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perf_set_pmu_inuse(1);
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
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@ -1007,11 +1120,10 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
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* things if requested. Note that interrupts are hard-disabled
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* here so there is no possibility of being interrupted.
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*/
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static void record_and_restart(struct perf_counter *counter, long val,
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static void record_and_restart(struct perf_counter *counter, unsigned long val,
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struct pt_regs *regs, int nmi)
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{
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u64 period = counter->hw.sample_period;
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unsigned long mmcra, sdsync;
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s64 prev, delta, left;
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int record = 0;
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@ -1033,8 +1145,8 @@ static void record_and_restart(struct perf_counter *counter, long val,
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left = period;
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record = 1;
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}
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if (left < 0x80000000L)
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val = 0x80000000L - left;
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if (left < 0x80000000LL)
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val = 0x80000000LL - left;
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}
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/*
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@ -1047,22 +1159,9 @@ static void record_and_restart(struct perf_counter *counter, long val,
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.period = counter->hw.last_period,
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};
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if (counter->attr.sample_type & PERF_SAMPLE_ADDR) {
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/*
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* The user wants a data address recorded.
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* If we're not doing instruction sampling,
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* give them the SDAR (sampled data address).
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* If we are doing instruction sampling, then only
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* give them the SDAR if it corresponds to the
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* instruction pointed to by SIAR; this is indicated
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* by the [POWER6_]MMCRA_SDSYNC bit in MMCRA.
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*/
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mmcra = regs->dsisr;
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sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
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POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
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if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
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data.addr = mfspr(SPRN_SDAR);
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}
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if (counter->attr.sample_type & PERF_SAMPLE_ADDR)
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perf_get_data_addr(regs, &data.addr);
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if (perf_counter_overflow(counter, nmi, &data)) {
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/*
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* Interrupts are coming too fast - throttle them
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@ -1088,25 +1187,12 @@ static void record_and_restart(struct perf_counter *counter, long val,
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*/
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unsigned long perf_misc_flags(struct pt_regs *regs)
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{
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unsigned long mmcra;
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u32 flags = perf_get_misc_flags(regs);
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if (TRAP(regs) != 0xf00) {
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/* not a PMU interrupt */
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return user_mode(regs) ? PERF_EVENT_MISC_USER :
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PERF_EVENT_MISC_KERNEL;
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}
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mmcra = regs->dsisr;
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if (ppmu->flags & PPMU_ALT_SIPR) {
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if (mmcra & POWER6_MMCRA_SIHV)
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return PERF_EVENT_MISC_HYPERVISOR;
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return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
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PERF_EVENT_MISC_KERNEL;
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}
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if (mmcra & MMCRA_SIHV)
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return PERF_EVENT_MISC_HYPERVISOR;
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return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
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PERF_EVENT_MISC_KERNEL;
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if (flags)
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return flags;
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return user_mode(regs) ? PERF_EVENT_MISC_USER :
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PERF_EVENT_MISC_KERNEL;
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}
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/*
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@ -1115,20 +1201,12 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
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*/
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unsigned long perf_instruction_pointer(struct pt_regs *regs)
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{
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unsigned long mmcra;
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unsigned long ip;
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unsigned long slot;
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if (TRAP(regs) != 0xf00)
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return regs->nip; /* not a PMU interrupt */
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ip = mfspr(SPRN_SIAR);
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mmcra = regs->dsisr;
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if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
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slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
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if (slot > 1)
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ip += 4 * (slot - 1);
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}
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ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
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return ip;
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}
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@ -1140,7 +1218,7 @@ static void perf_counter_interrupt(struct pt_regs *regs)
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int i;
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struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
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struct perf_counter *counter;
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long val;
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unsigned long val;
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int found = 0;
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int nmi;
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@ -1148,16 +1226,9 @@ static void perf_counter_interrupt(struct pt_regs *regs)
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freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
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mfspr(SPRN_PMC6));
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/*
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* Overload regs->dsisr to store MMCRA so we only need to read it once.
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*/
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regs->dsisr = mfspr(SPRN_MMCRA);
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perf_read_regs(regs);
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/*
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* If interrupts were soft-disabled when this PMU interrupt
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* occurred, treat it as an NMI.
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*/
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nmi = !regs->softe;
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nmi = perf_intr_is_nmi(regs);
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if (nmi)
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nmi_enter();
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else
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@ -1223,11 +1294,13 @@ int register_power_pmu(struct power_pmu *pmu)
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pr_info("%s performance monitor hardware support registered\n",
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pmu->name);
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#ifdef MSR_HV
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/*
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* Use FCHV to ignore kernel events if MSR.HV is set.
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*/
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if (mfmsr() & MSR_HV)
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freeze_counters_kernel = MMCR0_FCHV;
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#endif /* CONFIG_PPC64 */
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return 0;
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}
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