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drm/nouveau/clk: switch to instanced constructor 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 10:58:58 +10:00
parent d37766e560
commit 98fd7f8366
19 changed files with 128 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_clk *clk;
struct nvkm_devinit *devinit;
struct nvkm_fault *fault;
struct nvkm_fb *fb;
@ -144,7 +143,6 @@ struct nvkm_device_chip {
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
int (*devinit )(struct nvkm_device *, int idx, struct nvkm_devinit **);
int (*fault )(struct nvkm_device *, int idx, struct nvkm_fault **);
int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -3,3 +3,4 @@ NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VBIOS , struct nvkm_bios , bios)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BUS , struct nvkm_bus , bus)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_BAR , struct nvkm_bar , bar)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ACR , struct nvkm_acr , acr)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_CLK , struct nvkm_clk , clk)

20
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
View File

@ -125,14 +125,14 @@ int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);
int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
int nv04_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int nv40_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int nv50_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int g84_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int mcp77_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gt215_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_SUBDEV_CLK ] = "clk",
[NVKM_SUBDEV_DEVINIT ] = "devinit",
[NVKM_SUBDEV_FAULT ] = "fault",
[NVKM_SUBDEV_FB ] = "fb",

137
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -79,7 +79,7 @@ nv4_chipset = {
.name = "NV04",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv04_devinit_new,
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
@ -100,7 +100,7 @@ nv5_chipset = {
.name = "NV05",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv05_devinit_new,
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
@ -121,7 +121,7 @@ nv10_chipset = {
.name = "NV10",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -141,7 +141,7 @@ nv11_chipset = {
.name = "NV11",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -163,7 +163,7 @@ nv15_chipset = {
.name = "NV15",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -185,7 +185,7 @@ nv17_chipset = {
.name = "NV17",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -207,7 +207,7 @@ nv18_chipset = {
.name = "NV18",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -229,7 +229,7 @@ nv1a_chipset = {
.name = "nForce",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
@ -251,7 +251,7 @@ nv1f_chipset = {
.name = "nForce2",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
@ -273,7 +273,7 @@ nv20_chipset = {
.name = "NV20",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv20_fb_new,
.gpio = nv10_gpio_new,
@ -295,7 +295,7 @@ nv25_chipset = {
.name = "NV25",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
@ -317,7 +317,7 @@ nv28_chipset = {
.name = "NV28",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
@ -339,7 +339,7 @@ nv2a_chipset = {
.name = "NV2A",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
@ -361,7 +361,7 @@ nv30_chipset = {
.name = "NV30",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
@ -383,7 +383,7 @@ nv31_chipset = {
.name = "NV31",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
@ -406,7 +406,7 @@ nv34_chipset = {
.name = "NV34",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv10_devinit_new,
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
@ -429,7 +429,7 @@ nv35_chipset = {
.name = "NV35",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv04_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv35_fb_new,
.gpio = nv10_gpio_new,
@ -451,7 +451,7 @@ nv36_chipset = {
.name = "NV36",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv04_clk_new,
.clk = { 0x00000001, nv04_clk_new },
.devinit = nv20_devinit_new,
.fb = nv36_fb_new,
.gpio = nv10_gpio_new,
@ -474,7 +474,7 @@ nv40_chipset = {
.name = "NV40",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
@ -500,7 +500,7 @@ nv41_chipset = {
.name = "NV41",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
@ -526,7 +526,7 @@ nv42_chipset = {
.name = "NV42",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
@ -552,7 +552,7 @@ nv43_chipset = {
.name = "NV43",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
@ -578,7 +578,7 @@ nv44_chipset = {
.name = "NV44",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
@ -604,7 +604,7 @@ nv45_chipset = {
.name = "NV45",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
@ -630,7 +630,7 @@ nv46_chipset = {
.name = "G72",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
@ -656,7 +656,7 @@ nv47_chipset = {
.name = "G70",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv47_fb_new,
.gpio = nv10_gpio_new,
@ -682,7 +682,7 @@ nv49_chipset = {
.name = "G71",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
@ -708,7 +708,7 @@ nv4a_chipset = {
.name = "NV44A",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
@ -734,7 +734,7 @@ nv4b_chipset = {
.name = "G73",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
@ -760,7 +760,7 @@ nv4c_chipset = {
.name = "C61",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
@ -786,7 +786,7 @@ nv4e_chipset = {
.name = "C51",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv4e_fb_new,
.gpio = nv10_gpio_new,
@ -813,7 +813,7 @@ nv50_chipset = {
.bar = { 0x00000001, nv50_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv50_bus_new },
.clk = nv50_clk_new,
.clk = { 0x00000001, nv50_clk_new },
.devinit = nv50_devinit_new,
.fb = nv50_fb_new,
.fuse = nv50_fuse_new,
@ -841,7 +841,7 @@ nv63_chipset = {
.name = "C73",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
@ -867,7 +867,7 @@ nv67_chipset = {
.name = "C67",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
@ -893,7 +893,7 @@ nv68_chipset = {
.name = "C68",
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv31_bus_new },
.clk = nv40_clk_new,
.clk = { 0x00000001, nv40_clk_new },
.devinit = nv1a_devinit_new,
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
@ -920,7 +920,7 @@ nv84_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv50_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -952,7 +952,7 @@ nv86_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv50_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -984,7 +984,7 @@ nv92_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, nv50_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -1016,7 +1016,7 @@ nv94_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -1048,7 +1048,7 @@ nv96_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -1080,7 +1080,7 @@ nv98_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g98_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -1112,7 +1112,7 @@ nva0_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = g84_clk_new,
.clk = { 0x00000001, g84_clk_new },
.devinit = g84_devinit_new,
.fb = g84_fb_new,
.fuse = nv50_fuse_new,
@ -1144,7 +1144,7 @@ nva3_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = gt215_clk_new,
.clk = { 0x00000001, gt215_clk_new },
.devinit = gt215_devinit_new,
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
@ -1178,7 +1178,7 @@ nva5_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = gt215_clk_new,
.clk = { 0x00000001, gt215_clk_new },
.devinit = gt215_devinit_new,
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
@ -1211,7 +1211,7 @@ nva8_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = gt215_clk_new,
.clk = { 0x00000001, gt215_clk_new },
.devinit = gt215_devinit_new,
.fb = gt215_fb_new,
.fuse = nv50_fuse_new,
@ -1244,7 +1244,7 @@ nvaa_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = mcp77_clk_new,
.clk = { 0x00000001, mcp77_clk_new },
.devinit = g98_devinit_new,
.fb = mcp77_fb_new,
.fuse = nv50_fuse_new,
@ -1276,7 +1276,7 @@ nvac_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = mcp77_clk_new,
.clk = { 0x00000001, mcp77_clk_new },
.devinit = g98_devinit_new,
.fb = mcp77_fb_new,
.fuse = nv50_fuse_new,
@ -1308,7 +1308,7 @@ nvaf_chipset = {
.bar = { 0x00000001, g84_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, g94_bus_new },
.clk = gt215_clk_new,
.clk = { 0x00000001, gt215_clk_new },
.devinit = mcp89_devinit_new,
.fb = mcp89_fb_new,
.fuse = nv50_fuse_new,
@ -1341,7 +1341,7 @@ nvc0_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1378,7 +1378,7 @@ nvc1_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf108_fb_new,
.fuse = gf100_fuse_new,
@ -1414,7 +1414,7 @@ nvc3_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1450,7 +1450,7 @@ nvc4_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1487,7 +1487,7 @@ nvc8_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1524,7 +1524,7 @@ nvce_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1561,7 +1561,7 @@ nvcf_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1597,7 +1597,7 @@ nvd7_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1632,7 +1632,7 @@ nvd9_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gf100_clk_new,
.clk = { 0x00000001, gf100_clk_new },
.devinit = gf100_devinit_new,
.fb = gf100_fb_new,
.fuse = gf100_fuse_new,
@ -1668,7 +1668,7 @@ nve4_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
@ -1707,7 +1707,7 @@ nve6_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
@ -1746,7 +1746,7 @@ nve7_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk104_fb_new,
.fuse = gf100_fuse_new,
@ -1784,7 +1784,7 @@ nvea_chipset = {
.name = "GK20A",
.bar = { 0x00000001, gk20a_bar_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk20a_clk_new,
.clk = { 0x00000001, gk20a_clk_new },
.fb = gk20a_fb_new,
.fuse = gf100_fuse_new,
.ibus = gk20a_ibus_new,
@ -1810,7 +1810,7 @@ nvf0_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk110_fb_new,
.fuse = gf100_fuse_new,
@ -1848,7 +1848,7 @@ nvf1_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk110_fb_new,
.fuse = gf100_fuse_new,
@ -1886,7 +1886,7 @@ nv106_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk110_fb_new,
.fuse = gf100_fuse_new,
@ -1924,7 +1924,7 @@ nv108_chipset = {
.bar = { 0x00000001, gf100_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gf100_devinit_new,
.fb = gk110_fb_new,
.fuse = gf100_fuse_new,
@ -1962,7 +1962,7 @@ nv117_chipset = {
.bar = { 0x00000001, gm107_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gm107_devinit_new,
.fb = gm107_fb_new,
.fuse = gm107_fuse_new,
@ -1998,7 +1998,7 @@ nv118_chipset = {
.bar = { 0x00000001, gm107_bar_new },
.bios = { 0x00000001, nvkm_bios_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gk104_clk_new,
.clk = { 0x00000001, gk104_clk_new },
.devinit = gm107_devinit_new,
.fb = gm107_fb_new,
.fuse = gm107_fuse_new,
@ -2145,7 +2145,7 @@ nv12b_chipset = {
.acr = { 0x00000001, gm20b_acr_new },
.bar = { 0x00000001, gm20b_bar_new },
.bus = { 0x00000001, gf100_bus_new },
.clk = gm20b_clk_new,
.clk = { 0x00000001, gm20b_clk_new },
.fb = gm20b_fb_new,
.fuse = gm107_fuse_new,
.ibus = gk20a_ibus_new,
@ -3248,7 +3248,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_SUBDEV_CLK , clk);
_(NVKM_SUBDEV_DEVINIT , devinit);
_(NVKM_SUBDEV_FAULT , fault);
_(NVKM_SUBDEV_FB , fb);

8
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -649,7 +649,7 @@ nvkm_clk = {
int
nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
int index, bool allow_reclock, struct nvkm_clk *clk)
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk)
{
struct nvkm_subdev *subdev = &clk->subdev;
struct nvkm_bios *bios = device->bios;
@ -657,7 +657,7 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
const char *mode;
struct nvbios_vpstate_header h;
nvkm_subdev_ctor(&nvkm_clk, device, index, subdev);
nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev);
if (bios && !nvbios_vpstate_parse(bios, &h)) {
struct nvbios_vpstate_entry base, boost;
@ -716,9 +716,9 @@ nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
int
nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
int index, bool allow_reclock, struct nvkm_clk **pclk)
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
{
if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL)))
return -ENOMEM;
return nvkm_clk_ctor(func, device, index, allow_reclock, *pclk);
return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk);
}

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
View File

@ -41,8 +41,8 @@ g84_clk = {
};
int
g84_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
g84_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
return nv50_clk_new_(&g84_clk, device, index,
(device->chipset >= 0x94), pclk);
return nv50_clk_new_(&g84_clk, device, type, inst, (device->chipset >= 0x94), pclk);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
View File

@ -468,7 +468,8 @@ gf100_clk = {
};
int
gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
gf100_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gf100_clk *clk;
@ -476,5 +477,5 @@ gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
return -ENOMEM;
*pclk = &clk->base;
return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base);
return nvkm_clk_ctor(&gf100_clk, device, type, inst, false, &clk->base);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
View File

@ -504,7 +504,8 @@ gk104_clk = {
};
int
gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
gk104_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gk104_clk *clk;
@ -512,5 +513,5 @@ gk104_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
return -ENOMEM;
*pclk = &clk->base;
return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base);
return nvkm_clk_ctor(&gk104_clk, device, type, inst, true, &clk->base);
}

16
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
View File

@ -610,10 +610,9 @@ gk20a_clk = {
};
int
gk20a_clk_ctor(struct nvkm_device *device, int index,
const struct nvkm_clk_func *func,
const struct gk20a_clk_pllg_params *params,
struct gk20a_clk *clk)
gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
const struct nvkm_clk_func *func, const struct gk20a_clk_pllg_params *params,
struct gk20a_clk *clk)
{
struct nvkm_device_tegra *tdev = device->func->tegra(device);
int ret;
@ -628,7 +627,7 @@ gk20a_clk_ctor(struct nvkm_device *device, int index,
clk->params = params;
clk->parent_rate = clk_get_rate(tdev->clk);
ret = nvkm_clk_ctor(func, device, index, true, &clk->base);
ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);
if (ret)
return ret;
@ -639,7 +638,8 @@ gk20a_clk_ctor(struct nvkm_device *device, int index,
}
int
gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gk20a_clk *clk;
int ret;
@ -649,11 +649,9 @@ gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
return -ENOMEM;
*pclk = &clk->base;
ret = gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params,
clk);
ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk);
clk->pl_to_div = pl_to_div;
clk->div_to_pl = div_to_pl;
return ret;
}

4
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
View File

@ -146,8 +146,8 @@ gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
clk->parent_rate / KHZ);
}
int gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *,
const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *,
const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
void gk20a_clk_fini(struct nvkm_clk *);
int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);

17
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
View File

@ -908,7 +908,7 @@ gm20b_clk = {
};
static int
gm20b_clk_new_speedo0(struct nvkm_device *device, int index,
gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gk20a_clk *clk;
@ -919,12 +919,9 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, int index,
return -ENOMEM;
*pclk = &clk->base;
ret = gk20a_clk_ctor(device, index, &gm20b_clk_speedo0,
&gm20b_pllg_params, clk);
ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk_speedo0, &gm20b_pllg_params, clk);
clk->pl_to_div = pl_to_div;
clk->div_to_pl = div_to_pl;
return ret;
}
@ -1014,7 +1011,8 @@ gm20b_clk_init_safe_fmax(struct gm20b_clk *clk)
}
int
gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct nvkm_device_tegra *tdev = device->func->tegra(device);
struct gm20b_clk *clk;
@ -1024,7 +1022,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
/* Speedo 0 GPUs cannot use noise-aware PLL */
if (tdev->gpu_speedo_id == 0)
return gm20b_clk_new_speedo0(device, index, pclk);
return gm20b_clk_new_speedo0(device, type, inst, pclk);
/* Speedo >= 1, use NAPLL */
clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL);
@ -1036,8 +1034,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
/* duplicate the clock parameters since we will patch them below */
clk_params = (void *) (clk + 1);
*clk_params = gm20b_pllg_params;
ret = gk20a_clk_ctor(device, index, &gm20b_clk, clk_params,
&clk->base);
ret = gk20a_clk_ctor(device, type, inst, &gm20b_clk, clk_params, &clk->base);
if (ret)
return ret;
@ -1050,7 +1047,7 @@ gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
if (clk_params->max_m == 0) {
nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n");
kfree(clk);
return gm20b_clk_new_speedo0(device, index, pclk);
return gm20b_clk_new_speedo0(device, type, inst, pclk);
}
clk->base.pl_to_div = pl_to_div;

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
View File

@ -537,7 +537,8 @@ gt215_clk = {
};
int
gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
gt215_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct gt215_clk *clk;
@ -545,5 +546,5 @@ gt215_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
return -ENOMEM;
*pclk = &clk->base;
return nvkm_clk_ctor(&gt215_clk, device, index, true, &clk->base);
return nvkm_clk_ctor(&gt215_clk, device, type, inst, true, &clk->base);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
View File

@ -409,7 +409,8 @@ mcp77_clk = {
};
int
mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
mcp77_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct mcp77_clk *clk;
@ -417,5 +418,5 @@ mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
return -ENOMEM;
*pclk = &clk->base;
return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base);
return nvkm_clk_ctor(&mcp77_clk, device, type, inst, true, &clk->base);
}

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
View File

@ -72,9 +72,10 @@ nv04_clk = {
};
int
nv04_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
nv04_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
int ret = nvkm_clk_new_(&nv04_clk, device, index, false, pclk);
int ret = nvkm_clk_new_(&nv04_clk, device, type, inst, false, pclk);
if (ret == 0) {
(*pclk)->pll_calc = nv04_clk_pll_calc;
(*pclk)->pll_prog = nv04_clk_pll_prog;

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
View File

@ -218,7 +218,8 @@ nv40_clk = {
};
int
nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
nv40_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
struct nv40_clk *clk;
@ -228,5 +229,5 @@ nv40_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
clk->base.pll_prog = nv04_clk_pll_prog;
*pclk = &clk->base;
return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base);
return nvkm_clk_ctor(&nv40_clk, device, type, inst, true, &clk->base);
}

9
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
View File

@ -507,14 +507,14 @@ nv50_clk_tidy(struct nvkm_clk *base)
int
nv50_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
int index, bool allow_reclock, struct nvkm_clk **pclk)
enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
{
struct nv50_clk *clk;
int ret;
if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base);
ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);
*pclk = &clk->base;
if (ret)
return ret;
@ -555,7 +555,8 @@ nv50_clk = {
};
int
nv50_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_clk **pclk)
{
return nv50_clk_new_(&nv50_clk, device, index, false, pclk);
return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk);
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
View File

@ -20,7 +20,7 @@ struct nv50_clk {
struct nv50_clk_hwsq hwsq;
};
int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
int nv50_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
bool, struct nvkm_clk **);
int nv50_clk_read(struct nvkm_clk *, enum nv_clk_src);
int nv50_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);

4
drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h
View File

@ -16,9 +16,9 @@ struct nvkm_clk_func {
struct nvkm_domain domains[];
};
int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int,
int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
bool allow_reclock, struct nvkm_clk *);
int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
bool allow_reclock, struct nvkm_clk **);
int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,