mirror of https://gitee.com/openkylin/linux.git
drm/i915/dpll_mgr: switch to kernel types
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Minor checkpatch/whitespace fixes sprinkled on top of the changed lines. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b73aefabb757acf59896bd77dbb20c2e343c6e6d.1547629303.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
cbe974fb96
commit
990290d124
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@ -346,7 +346,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
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{
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const enum intel_dpll_id id = pll->info->id;
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intel_wakeref_t wakeref;
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uint32_t val;
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u32 val;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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POWER_DOMAIN_PLLS);
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@ -490,7 +490,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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u32 val;
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val = I915_READ(WRPLL_CTL(id));
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I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
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@ -500,7 +500,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
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static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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uint32_t val;
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u32 val;
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val = I915_READ(SPLL_CTL);
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I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
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@ -513,7 +513,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
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{
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const enum intel_dpll_id id = pll->info->id;
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intel_wakeref_t wakeref;
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uint32_t val;
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u32 val;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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POWER_DOMAIN_PLLS);
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@ -533,7 +533,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_dpll_hw_state *hw_state)
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{
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intel_wakeref_t wakeref;
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uint32_t val;
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u32 val;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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POWER_DOMAIN_PLLS);
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@ -639,11 +639,12 @@ static unsigned hsw_wrpll_get_budget_for_freq(int clock)
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return budget;
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}
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static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
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unsigned r2, unsigned n2, unsigned p,
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static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
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unsigned int r2, unsigned int n2,
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unsigned int p,
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struct hsw_wrpll_rnp *best)
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{
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uint64_t a, b, c, d, diff, diff_best;
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u64 a, b, c, d, diff, diff_best;
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/* No best (r,n,p) yet */
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if (best->p == 0) {
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@ -702,7 +703,7 @@ static void
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hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
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{
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uint64_t freq2k;
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u64 freq2k;
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unsigned p, n2, r2;
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struct hsw_wrpll_rnp best = { 0, 0, 0 };
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unsigned budget;
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@ -768,7 +769,7 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
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struct intel_crtc_state *crtc_state)
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{
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struct intel_shared_dpll *pll;
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uint32_t val;
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u32 val;
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unsigned int p, n2, r2;
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hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
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@ -930,7 +931,7 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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u32 val;
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val = I915_READ(DPLL_CTRL1);
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@ -995,7 +996,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state)
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{
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uint32_t val;
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u32 val;
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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intel_wakeref_t wakeref;
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@ -1035,7 +1036,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
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const struct skl_dpll_regs *regs = skl_dpll_regs;
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const enum intel_dpll_id id = pll->info->id;
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intel_wakeref_t wakeref;
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uint32_t val;
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u32 val;
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bool ret;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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@ -1062,9 +1063,9 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
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}
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struct skl_wrpll_context {
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uint64_t min_deviation; /* current minimal deviation */
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uint64_t central_freq; /* chosen central freq */
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uint64_t dco_freq; /* chosen dco freq */
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u64 min_deviation; /* current minimal deviation */
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u64 central_freq; /* chosen central freq */
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u64 dco_freq; /* chosen dco freq */
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unsigned int p; /* chosen divider */
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};
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@ -1080,11 +1081,11 @@ static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
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#define SKL_DCO_MAX_NDEVIATION 600
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static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
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uint64_t central_freq,
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uint64_t dco_freq,
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u64 central_freq,
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u64 dco_freq,
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unsigned int divider)
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{
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uint64_t deviation;
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u64 deviation;
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deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
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central_freq);
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@ -1158,21 +1159,21 @@ static void skl_wrpll_get_multipliers(unsigned int p,
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}
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struct skl_wrpll_params {
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uint32_t dco_fraction;
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uint32_t dco_integer;
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uint32_t qdiv_ratio;
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uint32_t qdiv_mode;
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uint32_t kdiv;
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uint32_t pdiv;
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uint32_t central_freq;
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u32 dco_fraction;
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u32 dco_integer;
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u32 qdiv_ratio;
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u32 qdiv_mode;
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u32 kdiv;
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u32 pdiv;
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u32 central_freq;
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};
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static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
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uint64_t afe_clock,
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uint64_t central_freq,
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uint32_t p0, uint32_t p1, uint32_t p2)
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u64 afe_clock,
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u64 central_freq,
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u32 p0, u32 p1, u32 p2)
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{
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uint64_t dco_freq;
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u64 dco_freq;
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switch (central_freq) {
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case 9600000000ULL:
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@ -1238,10 +1239,10 @@ static bool
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skl_ddi_calculate_wrpll(int clock /* in Hz */,
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struct skl_wrpll_params *wrpll_params)
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{
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uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
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uint64_t dco_central_freq[3] = {8400000000ULL,
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9000000000ULL,
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9600000000ULL};
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u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
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u64 dco_central_freq[3] = { 8400000000ULL,
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9000000000ULL,
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9600000000ULL };
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static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
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24, 28, 30, 32, 36, 40, 42, 44,
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48, 52, 54, 56, 60, 64, 66, 68,
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@ -1265,7 +1266,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
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for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
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for (i = 0; i < dividers[d].n_dividers; i++) {
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unsigned int p = dividers[d].list[i];
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uint64_t dco_freq = p * afe_clock;
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u64 dco_freq = p * afe_clock;
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skl_wrpll_try_divider(&ctx,
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dco_central_freq[dco],
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@ -1311,7 +1312,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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int clock)
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{
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uint32_t ctrl1, cfgcr1, cfgcr2;
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u32 ctrl1, cfgcr1, cfgcr2;
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struct skl_wrpll_params wrpll_params = { 0, };
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/*
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@ -1348,7 +1349,7 @@ static bool
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skl_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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uint32_t ctrl1;
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u32 ctrl1;
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/*
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* See comment in intel_dpll_hw_state to understand why we always use 0
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@ -1450,7 +1451,7 @@ static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
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static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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uint32_t temp;
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u32 temp;
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enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
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enum dpio_phy phy;
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enum dpio_channel ch;
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@ -1571,7 +1572,7 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
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uint32_t temp;
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u32 temp;
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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temp &= ~PORT_PLL_ENABLE;
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@ -1597,7 +1598,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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intel_wakeref_t wakeref;
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enum dpio_phy phy;
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enum dpio_channel ch;
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uint32_t val;
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u32 val;
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bool ret;
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bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
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@ -1669,12 +1670,12 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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/* bxt clock parameters */
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struct bxt_clk_div {
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int clock;
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uint32_t p1;
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uint32_t p2;
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uint32_t m2_int;
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uint32_t m2_frac;
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u32 p1;
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u32 p2;
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u32 m2_int;
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u32 m2_frac;
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bool m2_frac_en;
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uint32_t n;
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u32 n;
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int vco;
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};
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@ -1741,8 +1742,8 @@ static bool bxt_ddi_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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int vco = clk_div->vco;
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uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
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uint32_t lanestagger;
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u32 prop_coef, int_coef, gain_ctl, targ_cnt;
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u32 lanestagger;
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if (vco >= 6200000 && vco <= 6700000) {
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prop_coef = 4;
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@ -1891,7 +1892,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (INTEL_GEN(dev_priv) < 9) {
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uint32_t val = I915_READ(LCPLL_CTL);
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u32 val = I915_READ(LCPLL_CTL);
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/*
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* The LCPLL register should be turned on by the BIOS. For now
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@ -1977,7 +1978,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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u32 val;
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/* 1. Enable DPLL power in DPLL_ENABLE. */
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val = I915_READ(CNL_DPLL_ENABLE(id));
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@ -2052,7 +2053,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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const enum intel_dpll_id id = pll->info->id;
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uint32_t val;
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u32 val;
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/*
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* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
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@ -2110,7 +2111,7 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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{
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const enum intel_dpll_id id = pll->info->id;
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intel_wakeref_t wakeref;
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uint32_t val;
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u32 val;
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bool ret;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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@ -2246,7 +2247,7 @@ cnl_ddi_calculate_wrpll(int clock,
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struct skl_wrpll_params *wrpll_params)
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{
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u32 afe_clock = clock * 5;
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uint32_t ref_clock;
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u32 ref_clock;
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u32 dco_min = 7998000;
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u32 dco_max = 10000000;
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u32 dco_mid = (dco_min + dco_max) / 2;
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@ -2292,7 +2293,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
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int clock)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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uint32_t cfgcr0, cfgcr1;
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u32 cfgcr0, cfgcr1;
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struct skl_wrpll_params wrpll_params = { 0, };
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cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
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@ -2321,7 +2322,7 @@ static bool
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cnl_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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uint32_t cfgcr0;
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u32 cfgcr0;
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cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
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@ -2538,7 +2539,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
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struct intel_dpll_hw_state *pll_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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uint32_t cfgcr0, cfgcr1;
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u32 cfgcr0, cfgcr1;
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struct skl_wrpll_params pll_params = { 0 };
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bool ret;
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@ -2568,10 +2569,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
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}
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int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
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uint32_t pll_id)
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u32 pll_id)
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{
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uint32_t cfgcr0, cfgcr1;
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uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
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u32 cfgcr0, cfgcr1;
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u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
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const struct skl_wrpll_params *params;
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int index, n_entries, link_clock;
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@ -2654,10 +2655,10 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id)
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}
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static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
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uint32_t *target_dco_khz,
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u32 *target_dco_khz,
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struct intel_dpll_hw_state *state)
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{
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uint32_t dco_min_freq, dco_max_freq;
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u32 dco_min_freq, dco_max_freq;
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int div1_vals[] = {7, 5, 3, 2};
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unsigned int i;
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int div2;
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@ -2733,12 +2734,12 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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int refclk_khz = dev_priv->cdclk.hw.ref;
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uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
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uint32_t iref_ndiv, iref_trim, iref_pulse_w;
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uint32_t prop_coeff, int_coeff;
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uint32_t tdc_targetcnt, feedfwgain;
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uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
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uint64_t tmp;
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u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
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u32 iref_ndiv, iref_trim, iref_pulse_w;
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u32 prop_coeff, int_coeff;
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u32 tdc_targetcnt, feedfwgain;
|
||||
u64 ssc_stepsize, ssc_steplen, ssc_steplog;
|
||||
u64 tmp;
|
||||
bool use_ssc = false;
|
||||
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
|
||||
|
||||
|
|
@ -2761,7 +2762,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
|
|||
}
|
||||
m2div_rem = dco_khz % (refclk_khz * m1div);
|
||||
|
||||
tmp = (uint64_t)m2div_rem * (1 << 22);
|
||||
tmp = (u64)m2div_rem * (1 << 22);
|
||||
do_div(tmp, refclk_khz * m1div);
|
||||
m2div_frac = tmp;
|
||||
|
||||
|
|
@ -2820,11 +2821,11 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
|
|||
}
|
||||
|
||||
if (use_ssc) {
|
||||
tmp = (uint64_t)dco_khz * 47 * 32;
|
||||
tmp = (u64)dco_khz * 47 * 32;
|
||||
do_div(tmp, refclk_khz * m1div * 10000);
|
||||
ssc_stepsize = tmp;
|
||||
|
||||
tmp = (uint64_t)dco_khz * 1000;
|
||||
tmp = (u64)dco_khz * 1000;
|
||||
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
|
||||
} else {
|
||||
ssc_stepsize = 0;
|
||||
|
|
@ -2974,7 +2975,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|||
intel_wakeref_t wakeref;
|
||||
bool ret = false;
|
||||
enum port port;
|
||||
uint32_t val;
|
||||
u32 val;
|
||||
|
||||
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
||||
POWER_DOMAIN_PLLS);
|
||||
|
|
@ -3101,7 +3102,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
|
||||
uint32_t val;
|
||||
u32 val;
|
||||
|
||||
val = I915_READ(enable_reg);
|
||||
val |= PLL_POWER_ENABLE;
|
||||
|
|
@ -3142,7 +3143,7 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
const enum intel_dpll_id id = pll->info->id;
|
||||
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
|
||||
uint32_t val;
|
||||
u32 val;
|
||||
|
||||
/* The first steps are done by intel_ddi_post_disable(). */
|
||||
|
||||
|
|
|
|||
|
|
@ -138,14 +138,14 @@ enum intel_dpll_id {
|
|||
|
||||
struct intel_dpll_hw_state {
|
||||
/* i9xx, pch plls */
|
||||
uint32_t dpll;
|
||||
uint32_t dpll_md;
|
||||
uint32_t fp0;
|
||||
uint32_t fp1;
|
||||
u32 dpll;
|
||||
u32 dpll_md;
|
||||
u32 fp0;
|
||||
u32 fp1;
|
||||
|
||||
/* hsw, bdw */
|
||||
uint32_t wrpll;
|
||||
uint32_t spll;
|
||||
u32 wrpll;
|
||||
u32 spll;
|
||||
|
||||
/* skl */
|
||||
/*
|
||||
|
|
@ -154,34 +154,33 @@ struct intel_dpll_hw_state {
|
|||
* the register. This allows us to easily compare the state to share
|
||||
* the DPLL.
|
||||
*/
|
||||
uint32_t ctrl1;
|
||||
u32 ctrl1;
|
||||
/* HDMI only, 0 when used for DP */
|
||||
uint32_t cfgcr1, cfgcr2;
|
||||
u32 cfgcr1, cfgcr2;
|
||||
|
||||
/* cnl */
|
||||
uint32_t cfgcr0;
|
||||
u32 cfgcr0;
|
||||
/* CNL also uses cfgcr1 */
|
||||
|
||||
/* bxt */
|
||||
uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
|
||||
pcsdw12;
|
||||
u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
|
||||
|
||||
/*
|
||||
* ICL uses the following, already defined:
|
||||
* uint32_t cfgcr0, cfgcr1;
|
||||
* u32 cfgcr0, cfgcr1;
|
||||
*/
|
||||
uint32_t mg_refclkin_ctl;
|
||||
uint32_t mg_clktop2_coreclkctl1;
|
||||
uint32_t mg_clktop2_hsclkctl;
|
||||
uint32_t mg_pll_div0;
|
||||
uint32_t mg_pll_div1;
|
||||
uint32_t mg_pll_lf;
|
||||
uint32_t mg_pll_frac_lock;
|
||||
uint32_t mg_pll_ssc;
|
||||
uint32_t mg_pll_bias;
|
||||
uint32_t mg_pll_tdc_coldst_bias;
|
||||
uint32_t mg_pll_bias_mask;
|
||||
uint32_t mg_pll_tdc_coldst_bias_mask;
|
||||
u32 mg_refclkin_ctl;
|
||||
u32 mg_clktop2_coreclkctl1;
|
||||
u32 mg_clktop2_hsclkctl;
|
||||
u32 mg_pll_div0;
|
||||
u32 mg_pll_div1;
|
||||
u32 mg_pll_lf;
|
||||
u32 mg_pll_frac_lock;
|
||||
u32 mg_pll_ssc;
|
||||
u32 mg_pll_bias;
|
||||
u32 mg_pll_tdc_coldst_bias;
|
||||
u32 mg_pll_bias_mask;
|
||||
u32 mg_pll_tdc_coldst_bias_mask;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -280,7 +279,7 @@ struct dpll_info {
|
|||
* Inform the state checker that the DPLL is kept enabled even if
|
||||
* not in use by any CRTC.
|
||||
*/
|
||||
uint32_t flags;
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -343,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
|
|||
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
struct intel_dpll_hw_state *hw_state);
|
||||
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
|
||||
uint32_t pll_id);
|
||||
u32 pll_id);
|
||||
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
|
||||
enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
|
||||
bool intel_dpll_is_combophy(enum intel_dpll_id id);
|
||||
|
|
|
|||
Loading…
Reference in New Issue