mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: add df perfmon regs and funcs for xgmi
v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
Alex Deucher
parent
5326ad54c5
commit
992af942a6
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@ -210,6 +210,7 @@ struct amdgpu_irq_src;
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struct amdgpu_fpriv;
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struct amdgpu_bo_va_mapping;
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struct amdgpu_atif;
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struct kfd_vm_fault_info;
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enum amdgpu_cp_irq {
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AMDGPU_CP_IRQ_GFX_EOP = 0,
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@ -688,6 +689,12 @@ struct amdgpu_df_funcs {
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u32 *flags);
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void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
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bool enable);
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int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
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int is_enable);
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int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
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int is_disable);
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void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
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uint64_t *count);
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};
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/* Define the HW IP blocks will be used in driver , add more if necessary */
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enum amd_hw_ip_block_type {
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@ -1096,6 +1103,9 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
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const u32 array_size);
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bool amdgpu_device_is_px(struct drm_device *dev);
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bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
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struct amdgpu_device *peer_adev);
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/* atpx handler */
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#if defined(CONFIG_VGA_SWITCHEROO)
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void amdgpu_register_atpx_handler(void);
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@ -105,6 +105,431 @@ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
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*flags |= AMD_CG_SUPPORT_DF_MGCG;
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}
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/* hold counter assignment per gpu struct */
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struct df_v3_6_event_mask {
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struct amdgpu_device gpu;
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uint64_t config_assign_mask[AMDGPU_DF_MAX_COUNTERS];
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};
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/* get assigned df perfmon ctr as int */
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static void df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
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uint64_t config,
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int *counter)
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{
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struct df_v3_6_event_mask *mask;
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int i;
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
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if ((config & 0x0FFFFFFUL) == mask->config_assign_mask[i]) {
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*counter = i;
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return;
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}
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}
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}
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/* get address based on counter assignment */
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static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
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uint64_t config,
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int is_ctrl,
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uint32_t *lo_base_addr,
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uint32_t *hi_base_addr)
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{
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int target_cntr = -1;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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if (target_cntr < 0)
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return;
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switch (target_cntr) {
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case 0:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo0 : smnPerfMonCtrLo0;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi0 : smnPerfMonCtrHi0;
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break;
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case 1:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo1 : smnPerfMonCtrLo1;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi1 : smnPerfMonCtrHi1;
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break;
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case 2:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo2 : smnPerfMonCtrLo2;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi2 : smnPerfMonCtrHi2;
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break;
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case 3:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo3 : smnPerfMonCtrLo3;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi3 : smnPerfMonCtrHi3;
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break;
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}
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}
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/* get read counter address */
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static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
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uint64_t config,
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uint32_t *lo_base_addr,
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uint32_t *hi_base_addr)
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{
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df_v3_6_pmc_get_addr(adev, config, 0, lo_base_addr, hi_base_addr);
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}
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/* get control counter settings i.e. address and values to set */
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static void df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
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uint64_t config,
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uint32_t *lo_base_addr,
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uint32_t *hi_base_addr,
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uint32_t *lo_val,
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uint32_t *hi_val)
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{
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uint32_t eventsel, instance, unitmask;
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uint32_t es_5_0, es_13_0, es_13_6, es_13_12, es_11_8, es_7_0;
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df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
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if (lo_val == NULL || hi_val == NULL)
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return;
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if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
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DRM_ERROR("DF PMC addressing not retrived! Lo: %x, Hi: %x",
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*lo_base_addr, *hi_base_addr);
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return;
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}
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eventsel = GET_EVENT(config);
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instance = GET_INSTANCE(config);
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unitmask = GET_UNITMASK(config);
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es_5_0 = eventsel & 0x3FUL;
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es_13_6 = instance;
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es_13_0 = (es_13_6 << 6) + es_5_0;
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es_13_12 = (es_13_0 & 0x03000UL) >> 12;
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es_11_8 = (es_13_0 & 0x0F00UL) >> 8;
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es_7_0 = es_13_0 & 0x0FFUL;
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*lo_val = (es_7_0 & 0xFFUL) | ((unitmask & 0x0FUL) << 8);
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*hi_val = (es_11_8 | ((es_13_12)<<(29)));
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}
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/* assign df performance counters for read */
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static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
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uint64_t config,
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int *is_assigned)
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{
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struct df_v3_6_event_mask *mask;
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int i, target_cntr;
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target_cntr = -1;
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*is_assigned = 0;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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if (target_cntr >= 0) {
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*is_assigned = 1;
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return 0;
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}
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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for (i = 0; i < AMDGPU_DF_MAX_COUNTERS; i++) {
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if (mask->config_assign_mask[i] == 0ULL) {
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mask->config_assign_mask[i] = config & 0x0FFFFFFUL;
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return 0;
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}
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}
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return -ENOSPC;
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}
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/* release performance counter */
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static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
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uint64_t config)
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{
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struct df_v3_6_event_mask *mask;
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int target_cntr;
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target_cntr = -1;
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df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
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mask = container_of(adev, struct df_v3_6_event_mask, gpu);
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if (target_cntr >= 0)
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mask->config_assign_mask[target_cntr] = 0ULL;
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}
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/*
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* get xgmi link counters via programmable data fabric (df) counters (max 4)
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* using cake tx event.
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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* @count -> counters to pass
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*
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*/
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static void df_v3_6_get_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance,
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uint64_t *count)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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uint64_t config;
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config = GET_INSTANCE_CONFIG(instance);
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df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
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&hi_base_addr);
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if ((lo_base_addr == 0) || (hi_base_addr == 0))
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return;
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lo_val = RREG32_PCIE(lo_base_addr);
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hi_val = RREG32_PCIE(hi_base_addr);
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*count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
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}
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/*
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* reset xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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*
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*/
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static void df_v3_6_reset_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance)
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{
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uint32_t lo_base_addr, hi_base_addr;
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uint64_t config;
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config = 0ULL | (0x7ULL) | ((0x46ULL + instance) << 8) | (0x2 << 16);
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df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
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&hi_base_addr);
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if ((lo_base_addr == 0) || (hi_base_addr == 0))
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return;
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WREG32_PCIE(lo_base_addr, 0UL);
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WREG32_PCIE(hi_base_addr, 0UL);
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}
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/*
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* add xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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*
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*/
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static int df_v3_6_add_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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uint64_t config;
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int ret, is_assigned;
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if (instance < 0 || instance > 1)
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return -EINVAL;
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config = GET_INSTANCE_CONFIG(instance);
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ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
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if (ret || is_assigned)
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return ret;
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df_v3_6_pmc_get_ctrl_settings(adev,
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config,
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&lo_base_addr,
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&hi_base_addr,
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&lo_val,
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&hi_val);
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WREG32_PCIE(lo_base_addr, lo_val);
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WREG32_PCIE(hi_base_addr, hi_val);
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return ret;
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}
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/*
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* start xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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* @is_enable -> either resume or assign event via df perfmon
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*
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*/
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static int df_v3_6_start_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance,
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int is_enable)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val;
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uint64_t config;
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int ret;
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if (instance < 0 || instance > 1)
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return -EINVAL;
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if (is_enable) {
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ret = df_v3_6_add_xgmi_link_cntr(adev, instance);
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if (ret)
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return ret;
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} else {
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config = GET_INSTANCE_CONFIG(instance);
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df_v3_6_pmc_get_ctrl_settings(adev,
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config,
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&lo_base_addr,
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&hi_base_addr,
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NULL,
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NULL);
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if (lo_base_addr == 0)
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return -EINVAL;
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lo_val = RREG32_PCIE(lo_base_addr);
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WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
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ret = 0;
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}
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return ret;
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}
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/*
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* start xgmi link counters
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*
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* @adev -> amdgpu device
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* @instance-> currently cake has 2 links to poll on vega20
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* @is_enable -> either pause or unassign event via df perfmon
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*
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*/
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static int df_v3_6_stop_xgmi_link_cntr(struct amdgpu_device *adev,
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int instance,
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int is_disable)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val;
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uint64_t config;
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config = GET_INSTANCE_CONFIG(instance);
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if (is_disable) {
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df_v3_6_reset_xgmi_link_cntr(adev, instance);
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df_v3_6_pmc_release_cntr(adev, config);
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} else {
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df_v3_6_pmc_get_ctrl_settings(adev,
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config,
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&lo_base_addr,
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&hi_base_addr,
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NULL,
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NULL);
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if ((lo_base_addr == 0) || (hi_base_addr == 0))
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return -EINVAL;
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lo_val = RREG32_PCIE(lo_base_addr);
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WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
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}
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return 0;
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}
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static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
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int is_enable)
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{
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int xgmi_tx_link, ret = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
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: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
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if (xgmi_tx_link >= 0)
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ret = df_v3_6_start_xgmi_link_cntr(adev, xgmi_tx_link,
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is_enable);
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if (ret)
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return ret;
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ret = 0;
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break;
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default:
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break;
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}
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return ret;
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}
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static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
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int is_disable)
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{
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int xgmi_tx_link, ret = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
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: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
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if (xgmi_tx_link >= 0) {
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ret = df_v3_6_stop_xgmi_link_cntr(adev,
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xgmi_tx_link,
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is_disable);
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if (ret)
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return ret;
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}
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ret = 0;
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break;
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default:
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break;
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}
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return ret;
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}
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static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
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uint64_t config,
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uint64_t *count)
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{
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int xgmi_tx_link;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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xgmi_tx_link = IS_DF_XGMI_0_TX(config) ? 0
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: (IS_DF_XGMI_1_TX(config) ? 1 : -1);
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if (xgmi_tx_link >= 0) {
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df_v3_6_reset_xgmi_link_cntr(adev, xgmi_tx_link);
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df_v3_6_get_xgmi_link_cntr(adev, xgmi_tx_link, count);
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}
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break;
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default:
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break;
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}
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}
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const struct amdgpu_df_funcs df_v3_6_funcs = {
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.init = df_v3_6_init,
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.enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
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@ -113,4 +538,7 @@ const struct amdgpu_df_funcs df_v3_6_funcs = {
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.update_medium_grain_clock_gating =
|
||||
df_v3_6_update_medium_grain_clock_gating,
|
||||
.get_clockgating_state = df_v3_6_get_clockgating_state,
|
||||
.pmc_start = df_v3_6_pmc_start,
|
||||
.pmc_stop = df_v3_6_pmc_stop,
|
||||
.pmc_get_count = df_v3_6_pmc_get_count
|
||||
};
|
||||
|
|
|
|||
|
|
@ -35,6 +35,23 @@ enum DF_V3_6_MGCG {
|
|||
DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY = 15
|
||||
};
|
||||
|
||||
/* Defined in global_features.h as FTI_PERFMON_VISIBLE */
|
||||
#define AMDGPU_DF_MAX_COUNTERS 4
|
||||
|
||||
/* get flags from df perfmon config */
|
||||
#define GET_EVENT(x) (x & 0xFFUL)
|
||||
#define GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
|
||||
#define GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
|
||||
#define GET_INSTANCE_CONFIG(x) (0ULL | (0x07ULL) \
|
||||
| ((0x046ULL + x) << 8) \
|
||||
| (0x02 << 16))
|
||||
|
||||
/* df event conf macros */
|
||||
#define IS_DF_XGMI_0_TX(x) (GET_EVENT(x) == 0x7 \
|
||||
&& GET_INSTANCE(x) == 0x46 && GET_UNITMASK(x) == 0x2)
|
||||
#define IS_DF_XGMI_1_TX(x) (GET_EVENT(x) == 0x7 \
|
||||
&& GET_INSTANCE(x) == 0x47 && GET_UNITMASK(x) == 0x2)
|
||||
|
||||
extern const struct amdgpu_df_funcs df_v3_6_funcs;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,4 +30,22 @@
|
|||
#define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044
|
||||
#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0
|
||||
|
||||
#define smnPerfMonCtlLo0 0x01d440UL
|
||||
#define smnPerfMonCtlHi0 0x01d444UL
|
||||
#define smnPerfMonCtlLo1 0x01d450UL
|
||||
#define smnPerfMonCtlHi1 0x01d454UL
|
||||
#define smnPerfMonCtlLo2 0x01d460UL
|
||||
#define smnPerfMonCtlHi2 0x01d464UL
|
||||
#define smnPerfMonCtlLo3 0x01d470UL
|
||||
#define smnPerfMonCtlHi3 0x01d474UL
|
||||
|
||||
#define smnPerfMonCtrLo0 0x01d448UL
|
||||
#define smnPerfMonCtrHi0 0x01d44cUL
|
||||
#define smnPerfMonCtrLo1 0x01d458UL
|
||||
#define smnPerfMonCtrHi1 0x01d45cUL
|
||||
#define smnPerfMonCtrLo2 0x01d468UL
|
||||
#define smnPerfMonCtrHi2 0x01d46cUL
|
||||
#define smnPerfMonCtrLo3 0x01d478UL
|
||||
#define smnPerfMonCtrHi3 0x01d47cUL
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue