mirror of https://gitee.com/openkylin/linux.git
mtd: gpmi: add EDO feature for imx6q
When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Huang Shijie
David Woodhouse
parent
e1ca95e3a9
commit
995fbbf563
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@ -737,6 +737,215 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
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return 0;
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}
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/*
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* <1> Firstly, we should know what's the GPMI-clock means.
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* The GPMI-clock is the internal clock in the gpmi nand controller.
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* If you set 100MHz to gpmi nand controller, the GPMI-clock's period
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* is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
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*
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* <2> Secondly, we should know what's the frequency on the nand chip pins.
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* The frequency on the nand chip pins is derived from the GPMI-clock.
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* We can get it from the following equation:
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*
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* F = G / (DS + DH)
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*
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* F : the frequency on the nand chip pins.
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* G : the GPMI clock, such as 100MHz.
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* DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
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* DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
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*
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* <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
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* the nand EDO(extended Data Out) timing could be applied.
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* The GPMI implements a feedback read strobe to sample the read data.
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* The feedback read strobe can be delayed to support the nand EDO timing
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* where the read strobe may deasserts before the read data is valid, and
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* read data is valid for some time after read strobe.
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*
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* The following figure illustrates some aspects of a NAND Flash read:
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*
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* |<---tREA---->|
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* | |
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* | | |
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* |<--tRP-->| |
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* | | |
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* __ ___|__________________________________
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* RDN \________/ |
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* |
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* /---------\
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* Read Data --------------< >---------
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* \---------/
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* | |
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* |<-D->|
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* FeedbackRDN ________ ____________
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* \___________/
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*
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* D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
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*
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*
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* <4> Now, we begin to describe how to compute the right RDN_DELAY.
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*
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* 4.1) From the aspect of the nand chip pins:
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* Delay = (tREA + C - tRP) {1}
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*
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* tREA : the maximum read access time. From the ONFI nand standards,
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* we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
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* Please check it in : www.onfi.org
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* C : a constant for adjust the delay. default is 4.
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* tRP : the read pulse width.
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* Specified by the HW_GPMI_TIMING0:DATA_SETUP:
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* tRP = (GPMI-clock-period) * DATA_SETUP
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*
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* 4.2) From the aspect of the GPMI nand controller:
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* Delay = RDN_DELAY * 0.125 * RP {2}
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*
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* RP : the DLL reference period.
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* if (GPMI-clock-period > DLL_THRETHOLD)
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* RP = GPMI-clock-period / 2;
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* else
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* RP = GPMI-clock-period;
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*
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* Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
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* is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
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* is 16ns, but in mx6q, we use 12ns.
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*
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* 4.3) since {1} equals {2}, we get:
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*
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* (tREA + 4 - tRP) * 8
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* RDN_DELAY = --------------------- {3}
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* RP
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*
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* 4.4) We only support the fastest asynchronous mode of ONFI nand.
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* For some ONFI nand, the mode 4 is the fastest mode;
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* while for some ONFI nand, the mode 5 is the fastest mode.
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* So we only support the mode 4 and mode 5. It is no need to
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* support other modes.
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*/
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static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
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struct gpmi_nfc_hardware_timing *hw)
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{
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struct resources *r = &this->resources;
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unsigned long rate = clk_get_rate(r->clock[0]);
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int mode = this->timing_mode;
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int dll_threshold = 16; /* in ns */
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unsigned long delay;
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unsigned long clk_period;
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int t_rea;
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int c = 4;
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int t_rp;
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int rp;
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/*
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* [1] for GPMI_HW_GPMI_TIMING0:
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* The async mode requires 40MHz for mode 4, 50MHz for mode 5.
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* The GPMI can support 100MHz at most. So if we want to
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* get the 40MHz or 50MHz, we have to set DS=1, DH=1.
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* Set the ADDRESS_SETUP to 0 in mode 4.
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*/
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hw->data_setup_in_cycles = 1;
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hw->data_hold_in_cycles = 1;
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hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0);
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/* [2] for GPMI_HW_GPMI_TIMING1 */
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hw->device_busy_timeout = 0x9000;
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/* [3] for GPMI_HW_GPMI_CTRL1 */
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hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
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if (GPMI_IS_MX6Q(this))
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dll_threshold = 12;
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/*
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* Enlarge 10 times for the numerator and denominator in {3}.
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* This make us to get more accurate result.
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*/
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clk_period = NSEC_PER_SEC / (rate / 10);
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dll_threshold *= 10;
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t_rea = ((mode == 5) ? 16 : 20) * 10;
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c *= 10;
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t_rp = clk_period * 1; /* DATA_SETUP is 1 */
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if (clk_period > dll_threshold) {
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hw->use_half_periods = 1;
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rp = clk_period / 2;
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} else {
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hw->use_half_periods = 0;
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rp = clk_period;
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}
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/*
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* Multiply the numerator with 10, we could do a round off:
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* 7.8 round up to 8; 7.4 round down to 7.
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*/
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delay = (((t_rea + c - t_rp) * 8) * 10) / rp;
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delay = (delay + 5) / 10;
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hw->sample_delay_factor = delay;
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}
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static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
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{
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struct resources *r = &this->resources;
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struct nand_chip *nand = &this->nand;
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struct mtd_info *mtd = &this->mtd;
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uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
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unsigned long rate;
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int ret;
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nand->select_chip(mtd, 0);
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/* [1] send SET FEATURE commond to NAND */
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feature[0] = mode;
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ret = nand->onfi_set_features(mtd, nand,
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ONFI_FEATURE_ADDR_TIMING_MODE, feature);
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if (ret)
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goto err_out;
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/* [2] send GET FEATURE command to double-check the timing mode */
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memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
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ret = nand->onfi_get_features(mtd, nand,
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ONFI_FEATURE_ADDR_TIMING_MODE, feature);
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if (ret || feature[0] != mode)
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goto err_out;
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nand->select_chip(mtd, -1);
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/* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
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rate = (mode == 5) ? 100000000 : 80000000;
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clk_set_rate(r->clock[0], rate);
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this->flags |= GPMI_ASYNC_EDO_ENABLED;
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this->timing_mode = mode;
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dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
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return 0;
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err_out:
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nand->select_chip(mtd, -1);
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dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
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return -EINVAL;
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}
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int gpmi_extra_init(struct gpmi_nand_data *this)
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{
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struct nand_chip *chip = &this->nand;
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/* Enable the asynchronous EDO feature. */
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if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
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int mode = onfi_get_async_timing_mode(chip);
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/* We only support the timing mode 4 and mode 5. */
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if (mode & ONFI_TIMING_MODE_5)
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mode = 5;
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else if (mode & ONFI_TIMING_MODE_4)
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mode = 4;
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else
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return 0;
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return enable_edo_mode(this, mode);
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}
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return 0;
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}
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/* Begin the I/O */
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void gpmi_begin(struct gpmi_nand_data *this)
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{
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@ -755,7 +964,10 @@ void gpmi_begin(struct gpmi_nand_data *this)
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goto err_out;
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}
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gpmi_nfc_compute_hardware_timing(this, &hw);
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if (this->flags & GPMI_ASYNC_EDO_ENABLED)
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gpmi_compute_edo_timing(this, &hw);
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else
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gpmi_nfc_compute_hardware_timing(this, &hw);
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/* [1] Set HW_GPMI_TIMING0 */
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reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
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@ -1517,6 +1517,14 @@ static int gpmi_scan_bbt(struct mtd_info *mtd)
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if (ret)
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return ret;
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/*
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* Can we enable the extra features? such as EDO or Sync mode.
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*
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* We do not check the return value now. That's means if we fail in
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* enable the extra features, we still can run in the normal way.
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*/
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gpmi_extra_init(this);
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/* use the default BBT implementation */
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return nand_default_bbt(mtd);
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}
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@ -122,6 +122,10 @@ struct nand_timing {
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};
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struct gpmi_nand_data {
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/* flags */
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#define GPMI_ASYNC_EDO_ENABLED (1 << 0)
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int flags;
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/* System Interface */
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struct device *dev;
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struct platform_device *pdev;
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@ -132,6 +136,7 @@ struct gpmi_nand_data {
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/* Flash Hardware */
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struct nand_timing timing;
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int timing_mode;
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/* BCH */
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struct bch_geometry bch_geometry;
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@ -259,6 +264,7 @@ extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
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/* GPMI-NAND helper function library */
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extern int gpmi_init(struct gpmi_nand_data *);
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extern int gpmi_extra_init(struct gpmi_nand_data *);
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extern void gpmi_clear_bch(struct gpmi_nand_data *);
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extern void gpmi_dump_info(struct gpmi_nand_data *);
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extern int bch_set_geometry(struct gpmi_nand_data *);
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