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[POWERPC] 4xx: Add L2 cache node to AMCC Taishan dts file 

This patch adds the L2 cache node to the Taishan 440GX dts file.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Stefan Roese 2008-03-26 22:42:55 +11:00 committed by Josh Boyer
parent 2a7069190e
commit 99d8be052e
1 changed files with 10 additions and 0 deletions
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10
arch/powerpc/boot/dts/taishan.dts
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@ -104,6 +104,16 @@ CPC0: cpc {
// FIXME: anything else?
};
L2C0: l2c {
compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
dcr-reg = <20 8 /* Internal SRAM DCR's */
30 8>; /* L2 cache DCR's */
cache-line-size = <20>; /* 32 bytes */
cache-size = <40000>; /* L2, 256K */
interrupt-parent = <&UIC2>;
interrupts = <17 1>;
};
plb {
compatible = "ibm,plb-440gx", "ibm,plb4";
#address-cells = <2>;