mirror of https://gitee.com/openkylin/linux.git
Davinci: gpio - structs and functions renamed
Renamed gpio types to something more sensible: struct gpio_controller --> struct davinci_gpio_regs struct davinci_gpio --> struct davinci_gpio_controller gpio2controller() --> gpio2regs() irq2controller() --> irq2regs() This change also moves davinci_gpio_controller definition to gpio.h. Eventually, the gpio registers structure will be moved to gpio.c and no longer a common cross-soc definition. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Cyril Chemparathy
Kevin Hilman
parent
ba4a984e83
commit
99e9e52de6
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@ -22,28 +22,22 @@
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static DEFINE_SPINLOCK(gpio_lock);
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struct davinci_gpio {
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struct gpio_chip chip;
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struct gpio_controller __iomem *regs;
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int irq_base;
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};
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio, chip)
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container_of(chip, struct davinci_gpio_controller, chip)
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static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
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static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
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/* create a non-inlined version */
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static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
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static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
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{
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return __gpio_to_controller(gpio);
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}
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static inline struct gpio_controller __iomem *irq2controller(int irq)
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static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
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{
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struct gpio_controller __iomem *g;
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struct davinci_gpio_regs __iomem *g;
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g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
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g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
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return g;
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}
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@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void);
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static inline int __davinci_direction(struct gpio_chip *chip,
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unsigned offset, bool out, int value)
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{
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struct davinci_gpio *d = chip2controller(chip);
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struct gpio_controller __iomem *g = d->regs;
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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u32 temp;
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u32 mask = 1 << offset;
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@ -99,8 +93,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
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*/
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static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio *d = chip2controller(chip);
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struct gpio_controller __iomem *g = d->regs;
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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return (1 << offset) & __raw_readl(&g->in_data);
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}
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@ -111,8 +105,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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static void
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davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct davinci_gpio *d = chip2controller(chip);
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struct gpio_controller __iomem *g = d->regs;
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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@ -150,7 +144,7 @@ static int __init davinci_gpio_setup(void)
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if (chips[i].chip.ngpio > 32)
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chips[i].chip.ngpio = 32;
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chips[i].regs = gpio2controller(base);
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chips[i].regs = gpio2regs(base);
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gpiochip_add(&chips[i].chip);
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}
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@ -174,7 +168,7 @@ pure_initcall(davinci_gpio_setup);
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static void gpio_irq_disable(unsigned irq)
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{
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struct gpio_controller __iomem *g = irq2controller(irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(irq);
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u32 mask = (u32) get_irq_data(irq);
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__raw_writel(mask, &g->clr_falling);
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@ -183,7 +177,7 @@ static void gpio_irq_disable(unsigned irq)
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static void gpio_irq_enable(unsigned irq)
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{
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struct gpio_controller __iomem *g = irq2controller(irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(irq);
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u32 mask = (u32) get_irq_data(irq);
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unsigned status = irq_desc[irq].status;
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@ -199,7 +193,7 @@ static void gpio_irq_enable(unsigned irq)
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static int gpio_irq_type(unsigned irq, unsigned trigger)
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{
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struct gpio_controller __iomem *g = irq2controller(irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(irq);
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u32 mask = (u32) get_irq_data(irq);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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@ -228,7 +222,7 @@ static struct irq_chip gpio_irqchip = {
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct gpio_controller __iomem *g = irq2controller(irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(irq);
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u32 mask = 0xffff;
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/* we only care about one bank */
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@ -266,7 +260,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio *d = chip2controller(chip);
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struct davinci_gpio_controller *d = chip2controller(chip);
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if (d->irq_base >= 0)
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return d->irq_base + offset;
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@ -289,7 +283,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
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{
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struct gpio_controller __iomem *g = irq2controller(irq);
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struct davinci_gpio_regs __iomem *g = irq2regs(irq);
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u32 mask = (u32) get_irq_data(irq);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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@ -318,7 +312,7 @@ static int __init davinci_gpio_irq_setup(void)
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u32 binten = 0;
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unsigned ngpio, bank_irq;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct gpio_controller __iomem *g;
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struct davinci_gpio_regs __iomem *g;
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ngpio = soc_info->gpio_num;
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@ -367,7 +361,7 @@ static int __init davinci_gpio_irq_setup(void)
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gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
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/* default trigger: both edges */
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g = gpio2controller(0);
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g = gpio2regs(0);
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__raw_writel(~0, &g->set_falling);
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__raw_writel(~0, &g->set_rising);
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@ -392,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
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unsigned i;
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/* disabled by default, enabled only as needed */
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g = gpio2controller(gpio);
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g = gpio2regs(gpio);
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__raw_writel(~0, &g->clr_falling);
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__raw_writel(~0, &g->clr_rising);
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@ -45,7 +45,7 @@
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/* Convert GPIO signal to GPIO pin number */
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#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
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struct gpio_controller {
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struct davinci_gpio_regs {
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u32 dir;
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u32 out_data;
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u32 set_data;
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@ -58,6 +58,12 @@ struct gpio_controller {
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u32 intstat;
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};
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struct davinci_gpio_controller {
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struct davinci_gpio_regs __iomem *regs;
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struct gpio_chip chip;
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int irq_base;
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};
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/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
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* with constant parameters; or in outlined code they execute at runtime.
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*
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@ -67,7 +73,7 @@ struct gpio_controller {
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*
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* These are NOT part of the cross-platform GPIO interface
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*/
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static inline struct gpio_controller __iomem *
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static inline struct davinci_gpio_regs __iomem *
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__gpio_to_controller(unsigned gpio)
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{
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void __iomem *ptr;
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@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio)
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
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struct gpio_controller __iomem *g;
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struct davinci_gpio_regs __iomem *g;
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u32 mask;
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g = __gpio_to_controller(gpio);
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@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
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*/
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static inline int gpio_get_value(unsigned gpio)
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{
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struct gpio_controller __iomem *g;
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struct davinci_gpio_regs __iomem *g;
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if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
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return __gpio_get_value(gpio);
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