mirror of https://gitee.com/openkylin/linux.git
Blackfin: make hardware trace output a little more useful
Decode the vast majority of insns that appear in the trace buffer to get a better idea of what's going on at a glance. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Robin Getz
Mike Frysinger
parent
d60805ad47
commit
9a95e2f100
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@ -25,10 +25,10 @@ extern unsigned long trace_buff_offset;
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extern unsigned long software_trace_buff[];
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#if defined(CONFIG_DEBUG_VERBOSE)
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extern void decode_address(char *buf, unsigned long address);
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extern bool get_instruction(unsigned short *val, unsigned short *address);
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extern bool get_instruction(unsigned int *val, unsigned short *address);
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#else
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#define decode_address(buf, address)
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#define get_instruction(val, address) 0
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static inline void decode_address(char *buf, unsigned long address) { }
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static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
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#endif
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/* Trace Macros for C files */
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@ -18,21 +18,14 @@
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*/
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static bool is_bfin_call(unsigned short *addr)
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{
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unsigned short opcode = 0, *ins_addr;
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ins_addr = (unsigned short *)addr;
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unsigned int opcode;
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if (!get_instruction(&opcode, ins_addr))
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if (!get_instruction(&opcode, addr))
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return false;
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if ((opcode >= 0x0060 && opcode <= 0x0067) ||
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(opcode >= 0x0070 && opcode <= 0x0077))
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return true;
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ins_addr--;
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if (!get_instruction(&opcode, ins_addr))
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return false;
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if (opcode >= 0xE300 && opcode <= 0xE3FF)
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(opcode >= 0x0070 && opcode <= 0x0077) ||
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(opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
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return true;
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return false;
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@ -75,6 +75,26 @@ void decode_address(char *buf, unsigned long address)
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} else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
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strcat(buf, "/* on-chip L1 ROM */");
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return;
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} else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
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strcat(buf, "/* on-chip scratchpad */");
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return;
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} else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
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strcat(buf, "/* unconnected memory */");
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return;
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} else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
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strcat(buf, "/* reserved memory */");
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return;
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} else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
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strcat(buf, "/* on-chip Data Bank A */");
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return;
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} else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
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strcat(buf, "/* on-chip Data Bank B */");
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return;
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}
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/*
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@ -173,7 +193,7 @@ void decode_address(char *buf, unsigned long address)
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* Similar to get_user, do some address checking, then dereference
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* Return true on success, false on bad address
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*/
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bool get_instruction(unsigned short *val, unsigned short *address)
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bool get_mem16(unsigned short *val, unsigned short *address)
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{
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unsigned long addr = (unsigned long)address;
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@ -181,10 +201,6 @@ bool get_instruction(unsigned short *val, unsigned short *address)
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if (addr & 0x1)
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return false;
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/* MMR region will never have instructions */
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if (addr >= SYSMMR_BASE)
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return false;
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switch (bfin_mem_access_type(addr, 2)) {
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case BFIN_MEM_ACCESS_CORE:
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case BFIN_MEM_ACCESS_CORE_ONLY:
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@ -201,60 +217,430 @@ bool get_instruction(unsigned short *val, unsigned short *address)
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}
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}
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bool get_instruction(unsigned int *val, unsigned short *address)
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{
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unsigned long addr = (unsigned long)address;
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unsigned short opcode0, opcode1;
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/* Check for odd addresses */
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if (addr & 0x1)
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return false;
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/* MMR region will never have instructions */
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if (addr >= SYSMMR_BASE)
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return false;
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/* Scratchpad will never have instructions */
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if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
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return false;
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/* Data banks will never have instructions */
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if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
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return false;
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if (!get_mem16(&opcode0, address))
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return false;
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/* was this a 32-bit instruction? If so, get the next 16 bits */
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if ((opcode0 & 0xc000) == 0xc000) {
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if (!get_mem16(&opcode1, address + 1))
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return false;
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*val = (opcode0 << 16) + opcode1;
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} else
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*val = opcode0;
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return true;
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}
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#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
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/*
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* decode the instruction if we are printing out the trace, as it
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* makes things easier to follow, without running it through objdump
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* These are the normal instructions which cause change of flow, which
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* would be at the source of the trace buffer
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* Decode the change of flow, and the common load/store instructions
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* which are the main cause for faults, and discontinuities in the trace
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* buffer.
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*/
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#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
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static void decode_instruction(unsigned short *address)
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{
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unsigned short opcode;
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if (get_instruction(&opcode, address)) {
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if (opcode == 0x0010)
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#define ProgCtrl_opcode 0x0000
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#define ProgCtrl_poprnd_bits 0
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#define ProgCtrl_poprnd_mask 0xf
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#define ProgCtrl_prgfunc_bits 4
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#define ProgCtrl_prgfunc_mask 0xf
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#define ProgCtrl_code_bits 8
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#define ProgCtrl_code_mask 0xff
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static void decode_ProgCtrl_0(unsigned int opcode)
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{
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int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
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int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
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if (prgfunc == 0 && poprnd == 0)
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pr_cont("NOP");
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else if (prgfunc == 1 && poprnd == 0)
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pr_cont("RTS");
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else if (opcode == 0x0011)
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else if (prgfunc == 1 && poprnd == 1)
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pr_cont("RTI");
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else if (opcode == 0x0012)
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else if (prgfunc == 1 && poprnd == 2)
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pr_cont("RTX");
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else if (opcode == 0x0013)
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else if (prgfunc == 1 && poprnd == 3)
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pr_cont("RTN");
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else if (opcode == 0x0014)
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else if (prgfunc == 1 && poprnd == 4)
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pr_cont("RTE");
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else if (opcode == 0x0025)
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else if (prgfunc == 2 && poprnd == 0)
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pr_cont("IDLE");
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else if (prgfunc == 2 && poprnd == 3)
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pr_cont("CSYNC");
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else if (prgfunc == 2 && poprnd == 4)
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pr_cont("SSYNC");
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else if (prgfunc == 2 && poprnd == 5)
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pr_cont("EMUEXCPT");
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else if (opcode >= 0x0040 && opcode <= 0x0047)
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pr_cont("STI R%i", opcode & 7);
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else if (opcode >= 0x0050 && opcode <= 0x0057)
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pr_cont("JUMP (P%i)", opcode & 7);
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else if (opcode >= 0x0060 && opcode <= 0x0067)
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pr_cont("CALL (P%i)", opcode & 7);
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else if (opcode >= 0x0070 && opcode <= 0x0077)
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pr_cont("CALL (PC+P%i)", opcode & 7);
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else if (opcode >= 0x0080 && opcode <= 0x0087)
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pr_cont("JUMP (PC+P%i)", opcode & 7);
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else if (opcode >= 0x0090 && opcode <= 0x009F)
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pr_cont("RAISE 0x%x", opcode & 0xF);
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else if (opcode >= 0x00A0 && opcode <= 0x00AF)
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pr_cont("EXCPT 0x%x", opcode & 0xF);
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else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF))
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pr_cont("IF !CC JUMP");
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else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff))
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pr_cont("IF CC JUMP");
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else if (opcode >= 0x2000 && opcode <= 0x2fff)
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pr_cont("JUMP.S");
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else if (opcode >= 0xe080 && opcode <= 0xe0ff)
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pr_cont("LSETUP");
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else if (opcode >= 0xe200 && opcode <= 0xe2ff)
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pr_cont("JUMP.L");
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else if (opcode >= 0xe300 && opcode <= 0xe3ff)
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pr_cont("CALL pcrel");
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else if (prgfunc == 3)
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pr_cont("CLI R%i", poprnd);
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else if (prgfunc == 4)
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pr_cont("STI R%i", poprnd);
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else if (prgfunc == 5)
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pr_cont("JUMP (P%i)", poprnd);
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else if (prgfunc == 6)
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pr_cont("CALL (P%i)", poprnd);
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else if (prgfunc == 7)
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pr_cont("CALL (PC + P%i)", poprnd);
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else if (prgfunc == 8)
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pr_cont("JUMP (PC + P%i", poprnd);
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else if (prgfunc == 9)
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pr_cont("RAISE %i", poprnd);
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else if (prgfunc == 10)
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pr_cont("EXCPT %i", poprnd);
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else
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pr_cont("0x%04x", opcode);
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}
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#define BRCC_opcode 0x1000
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#define BRCC_offset_bits 0
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#define BRCC_offset_mask 0x3ff
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#define BRCC_B_bits 10
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#define BRCC_B_mask 0x1
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#define BRCC_T_bits 11
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#define BRCC_T_mask 0x1
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#define BRCC_code_bits 12
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#define BRCC_code_mask 0xf
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static void decode_BRCC_0(unsigned int opcode)
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{
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int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
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int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
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pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
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}
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#define CALLa_opcode 0xe2000000
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#define CALLa_addr_bits 0
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#define CALLa_addr_mask 0xffffff
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#define CALLa_S_bits 24
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#define CALLa_S_mask 0x1
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#define CALLa_code_bits 25
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#define CALLa_code_mask 0x7f
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static void decode_CALLa_0(unsigned int opcode)
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{
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int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
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if (S)
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pr_cont("CALL pcrel");
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else
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pr_cont("JUMP.L");
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}
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#define LoopSetup_opcode 0xe0800000
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#define LoopSetup_eoffset_bits 0
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#define LoopSetup_eoffset_mask 0x3ff
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#define LoopSetup_dontcare_bits 10
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#define LoopSetup_dontcare_mask 0x3
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#define LoopSetup_reg_bits 12
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#define LoopSetup_reg_mask 0xf
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#define LoopSetup_soffset_bits 16
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#define LoopSetup_soffset_mask 0xf
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#define LoopSetup_c_bits 20
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#define LoopSetup_c_mask 0x1
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#define LoopSetup_rop_bits 21
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#define LoopSetup_rop_mask 0x3
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#define LoopSetup_code_bits 23
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#define LoopSetup_code_mask 0x1ff
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static void decode_LoopSetup_0(unsigned int opcode)
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{
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int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
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int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
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int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
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pr_cont("LSETUP <> LC%i", c);
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if ((rop & 1) == 1)
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pr_cont("= P%i", reg);
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if ((rop & 2) == 2)
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pr_cont(" >> 0x1");
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}
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#define DspLDST_opcode 0x9c00
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#define DspLDST_reg_bits 0
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#define DspLDST_reg_mask 0x7
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#define DspLDST_i_bits 3
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#define DspLDST_i_mask 0x3
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#define DspLDST_m_bits 5
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#define DspLDST_m_mask 0x3
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#define DspLDST_aop_bits 7
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#define DspLDST_aop_mask 0x3
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#define DspLDST_W_bits 9
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#define DspLDST_W_mask 0x1
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#define DspLDST_code_bits 10
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#define DspLDST_code_mask 0x3f
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static void decode_dspLDST_0(unsigned int opcode)
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{
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int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
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int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
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int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
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int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
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int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
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if (W == 0) {
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pr_cont("R%i", reg);
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switch (m) {
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case 0:
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pr_cont(" = ");
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break;
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case 1:
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pr_cont(".L = ");
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break;
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case 2:
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pr_cont(".W = ");
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break;
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}
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}
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pr_cont("[ I%i", i);
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switch (aop) {
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case 0:
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pr_cont("++ ]");
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break;
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case 1:
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pr_cont("-- ]");
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break;
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}
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if (W == 1) {
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pr_cont(" = R%i", reg);
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switch (m) {
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case 1:
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pr_cont(".L = ");
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break;
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case 2:
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pr_cont(".W = ");
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break;
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}
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}
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}
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#define LDST_opcode 0x9000
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#define LDST_reg_bits 0
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#define LDST_reg_mask 0x7
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#define LDST_ptr_bits 3
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#define LDST_ptr_mask 0x7
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#define LDST_Z_bits 6
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#define LDST_Z_mask 0x1
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#define LDST_aop_bits 7
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#define LDST_aop_mask 0x3
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#define LDST_W_bits 9
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#define LDST_W_mask 0x1
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#define LDST_sz_bits 10
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#define LDST_sz_mask 0x3
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#define LDST_code_bits 12
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#define LDST_code_mask 0xf
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static void decode_LDST_0(unsigned int opcode)
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{
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int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
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int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
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int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
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int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
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int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
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int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
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if (W == 0)
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pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
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switch (sz) {
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case 1:
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pr_cont("W");
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break;
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case 2:
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pr_cont("B");
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break;
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}
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pr_cont("[P%i", ptr);
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switch (aop) {
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case 0:
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pr_cont("++");
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break;
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case 1:
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pr_cont("--");
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break;
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}
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pr_cont("]");
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if (W == 1)
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pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
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if (sz) {
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if (Z)
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pr_cont(" (X)");
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else
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pr_cont(" (Z)");
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}
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}
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#define LDSTii_opcode 0xa000
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#define LDSTii_reg_bit 0
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#define LDSTii_reg_mask 0x7
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#define LDSTii_ptr_bit 3
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#define LDSTii_ptr_mask 0x7
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#define LDSTii_offset_bit 6
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#define LDSTii_offset_mask 0xf
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#define LDSTii_op_bit 10
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#define LDSTii_op_mask 0x3
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#define LDSTii_W_bit 12
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#define LDSTii_W_mask 0x1
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#define LDSTii_code_bit 13
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#define LDSTii_code_mask 0x7
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static void decode_LDSTii_0(unsigned int opcode)
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{
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int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
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int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
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int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
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int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
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int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
|
||||
|
||||
if (W == 0) {
|
||||
pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
|
||||
op == 1 || op == 2 ? "" : "W", ptr, offset);
|
||||
if (op == 2)
|
||||
pr_cont("(Z)");
|
||||
if (op == 3)
|
||||
pr_cont("(X)");
|
||||
} else {
|
||||
pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
|
||||
offset, op == 3 ? "P" : "R", reg);
|
||||
}
|
||||
}
|
||||
|
||||
#define LDSTidxI_opcode 0xe4000000
|
||||
#define LDSTidxI_offset_bits 0
|
||||
#define LDSTidxI_offset_mask 0xffff
|
||||
#define LDSTidxI_reg_bits 16
|
||||
#define LDSTidxI_reg_mask 0x7
|
||||
#define LDSTidxI_ptr_bits 19
|
||||
#define LDSTidxI_ptr_mask 0x7
|
||||
#define LDSTidxI_sz_bits 22
|
||||
#define LDSTidxI_sz_mask 0x3
|
||||
#define LDSTidxI_Z_bits 24
|
||||
#define LDSTidxI_Z_mask 0x1
|
||||
#define LDSTidxI_W_bits 25
|
||||
#define LDSTidxI_W_mask 0x1
|
||||
#define LDSTidxI_code_bits 26
|
||||
#define LDSTidxI_code_mask 0x3f
|
||||
|
||||
static void decode_LDSTidxI_0(unsigned int opcode)
|
||||
{
|
||||
int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
|
||||
int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
|
||||
int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
|
||||
int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
|
||||
int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
|
||||
int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
|
||||
|
||||
if (W == 0)
|
||||
pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
|
||||
|
||||
if (sz == 1)
|
||||
pr_cont("W");
|
||||
if (sz == 2)
|
||||
pr_cont("B");
|
||||
|
||||
pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
|
||||
(offset & 0x1f) << 2);
|
||||
|
||||
if (W == 0 && sz != 0) {
|
||||
if (Z)
|
||||
pr_cont("(X)");
|
||||
else
|
||||
pr_cont("(Z)");
|
||||
}
|
||||
|
||||
if (W == 1)
|
||||
pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
|
||||
|
||||
}
|
||||
|
||||
static void decode_opcode(unsigned int opcode)
|
||||
{
|
||||
#ifdef CONFIG_BUG
|
||||
if (opcode == BFIN_BUG_OPCODE)
|
||||
pr_cont("BUG");
|
||||
else
|
||||
#endif
|
||||
if ((opcode & 0xffffff00) == ProgCtrl_opcode)
|
||||
decode_ProgCtrl_0(opcode);
|
||||
else if ((opcode & 0xfffff000) == BRCC_opcode)
|
||||
decode_BRCC_0(opcode);
|
||||
else if ((opcode & 0xfffff000) == 0x2000)
|
||||
pr_cont("JUMP.S");
|
||||
else if ((opcode & 0xfe000000) == CALLa_opcode)
|
||||
decode_CALLa_0(opcode);
|
||||
else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
|
||||
decode_LoopSetup_0(opcode);
|
||||
else if ((opcode & 0xfffffc00) == DspLDST_opcode)
|
||||
decode_dspLDST_0(opcode);
|
||||
else if ((opcode & 0xfffff000) == LDST_opcode)
|
||||
decode_LDST_0(opcode);
|
||||
else if ((opcode & 0xffffe000) == LDSTii_opcode)
|
||||
decode_LDSTii_0(opcode);
|
||||
else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
|
||||
decode_LDSTidxI_0(opcode);
|
||||
else if (opcode & 0xffff0000)
|
||||
pr_cont("0x%08x", opcode);
|
||||
else
|
||||
pr_cont("0x%04x", opcode);
|
||||
}
|
||||
|
||||
#define BIT_MULTI_INS 0x08000000
|
||||
static void decode_instruction(unsigned short *address)
|
||||
{
|
||||
unsigned int opcode;
|
||||
|
||||
if (!get_instruction(&opcode, address))
|
||||
return;
|
||||
|
||||
decode_opcode(opcode);
|
||||
|
||||
/* If things are a 32-bit instruction, it has the possibility of being
|
||||
* a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
|
||||
* This test collidates with the unlink instruction, so disallow that
|
||||
*/
|
||||
if ((opcode & 0xc0000000) == 0xc0000000 &&
|
||||
(opcode & BIT_MULTI_INS) &&
|
||||
(opcode & 0xe8000000) != 0xe8000000) {
|
||||
pr_cont(" || ");
|
||||
if (!get_instruction(&opcode, address + 2))
|
||||
return;
|
||||
decode_opcode(opcode);
|
||||
pr_cont(" || ");
|
||||
if (!get_instruction(&opcode, address + 3))
|
||||
return;
|
||||
decode_opcode(opcode);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -397,7 +783,7 @@ void dump_bfin_mem(struct pt_regs *fp)
|
|||
if (!((unsigned long)addr & 0xF))
|
||||
pr_notice("0x%p: ", addr);
|
||||
|
||||
if (!get_instruction(&val, addr)) {
|
||||
if (!get_mem16(&val, addr)) {
|
||||
val = 0;
|
||||
sprintf(buf, "????");
|
||||
} else
|
||||
|
|
|
|||
|
|
@ -546,7 +546,7 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
|
|||
#ifdef CONFIG_BUG
|
||||
int is_valid_bugaddr(unsigned long addr)
|
||||
{
|
||||
unsigned short opcode;
|
||||
unsigned int opcode;
|
||||
|
||||
if (!get_instruction(&opcode, (unsigned short *)addr))
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue