mirror of https://gitee.com/openkylin/linux.git
nouveau, i915, vmwgfx and sun4i regression fixes
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaYVvmAAoJEAx081l5xIa+eTgP/AoA6c5Vi1y23o6TSk+ABvOQ 1YK4ZoIGhzliPj7cbTxgP9TH1rGjcjlwgkVvcnT10YMCA/CoHa+QY6TemUpew3v/ qo00D9rG92NxLWXamRyYiWWUHO96bFcqNyp4CBf8Wrrn0t1BCnQAmPLVAz9C5WcA 4DMXv1sjiD5CTJXxasS7bIMCUPPoQ0ZYUmJ93hUVt4gKWc88Ljl3ShigrhzwH04G NI0qxBPQ4khHJJ4v9las3gDALFRrqGp1IAp4lZutAKGcj3oZj6ypJkYzgGuZvLYZ zBMd8Z9HprGG7jfkxt2wmlJwVr3yjFDXMkhnx+4+DPSoAlScsW7VYvGZJpCIO7u3 E8zHcmpvmG3bsq8IiHw5P/4NBh6pPBh0En2QdtZFkeiGRXGcoF8eeywqp6y7Fr6i M8ml26+wy5NlKkB+ql8vAMhadf5j2STu1799DrpRZSOA8OyPG5hLVOyMBJgZKS5h DrMDJX7kJlcFzwDqM8LXqHat6Lsb4JASD3RsY0nyqppmb9QcM4gjg0Vpq6tB+rMP m2Fi15zG3J24fvFJlZAZED5hzYYFQLj+9Y7QEmZArPm78JzJ/OG7l0sxKZLwlmOP 8rQ8H4jzVyluNINFLlcH0jvs9iWWkfb41566KxkD3sFF8Arj7k+zF3x2CsROg1IH Bqp5DWfvf/D5cflKA81C =D+JQ -----END PGP SIGNATURE----- Merge tag 'drm-fixes-for-v4.15-rc9' of git://people.freedesktop.org/~airlied/linux Pull drm fixes from Dave Airlie: "Nouveau, i915, vmwgfx and sun4i regression fixes. The i915 change fixes a display corruption problem introduced in 4.15, the nouveau changes are for regressions in 4.15, one of the vmwgfx fixes goes back a little further, the other is a 4.15 regression fix, the 3 sun4i changes fix blank HDMI output on those devices" * tag 'drm-fixes-for-v4.15-rc9' of git://people.freedesktop.org/~airlied/linux: drm/nouveau/mmu/mcp77: fix regressions in stolen memory handling drm/nouveau/bar/gk20a: Avoid bar teardown during init drm/nouveau/drm/nouveau: Pass the proper arguments to nvif_object_map_handle() drm/vmwgfx: fix memory corruption with legacy/sou connectors drm/vmwgfx: Fix a boot time warning drm/i915: Fix deadlock in i830_disable_pipe() drm/i915: Redo plane sanitation during readout drm/i915: Add .get_hw_state() method for planes drm/sun4i: hdmi: Add missing rate halving check in sun4i_tmds_determine_rate drm/sun4i: hdmi: Fix incorrect assignment in sun4i_tmds_determine_rate drm/sun4i: hdmi: Check for unset best_parent in sun4i_tmds_determine_rate
This commit is contained in:
Linus Torvalds
commit
9abc937836
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@ -1211,23 +1211,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
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pipe_name(pipe));
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}
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static void assert_cursor(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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bool cur_state;
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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else
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cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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I915_STATE_WARN(cur_state != state,
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"cursor on pipe %c assertion failure (expected %s, current %s)\n",
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pipe_name(pipe), onoff(state), onoff(cur_state));
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}
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#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
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#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
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void assert_pipe(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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@ -1255,77 +1238,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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pipe_name(pipe), onoff(state), onoff(cur_state));
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}
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static void assert_plane(struct drm_i915_private *dev_priv,
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enum plane plane, bool state)
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static void assert_plane(struct intel_plane *plane, bool state)
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{
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u32 val;
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bool cur_state;
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bool cur_state = plane->get_hw_state(plane);
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val = I915_READ(DSPCNTR(plane));
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cur_state = !!(val & DISPLAY_PLANE_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"plane %c assertion failure (expected %s, current %s)\n",
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plane_name(plane), onoff(state), onoff(cur_state));
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"%s assertion failure (expected %s, current %s)\n",
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plane->base.name, onoff(state), onoff(cur_state));
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}
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#define assert_plane_enabled(d, p) assert_plane(d, p, true)
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#define assert_plane_disabled(d, p) assert_plane(d, p, false)
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#define assert_plane_enabled(p) assert_plane(p, true)
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#define assert_plane_disabled(p) assert_plane(p, false)
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static void assert_planes_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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static void assert_planes_disabled(struct intel_crtc *crtc)
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{
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int i;
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_plane *plane;
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/* Primary planes are fixed to pipes on gen4+ */
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if (INTEL_GEN(dev_priv) >= 4) {
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u32 val = I915_READ(DSPCNTR(pipe));
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I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
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"plane %c assertion failure, should be disabled but not\n",
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plane_name(pipe));
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return;
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}
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/* Need to check both planes against the pipe */
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for_each_pipe(dev_priv, i) {
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u32 val = I915_READ(DSPCNTR(i));
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enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
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DISPPLANE_SEL_PIPE_SHIFT;
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I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
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"plane %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(i), pipe_name(pipe));
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}
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}
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static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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int sprite;
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if (INTEL_GEN(dev_priv) >= 9) {
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for_each_sprite(dev_priv, pipe, sprite) {
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u32 val = I915_READ(PLANE_CTL(pipe, sprite));
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I915_STATE_WARN(val & PLANE_CTL_ENABLE,
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"plane %d assertion failure, should be off on pipe %c but is still active\n",
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sprite, pipe_name(pipe));
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}
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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for_each_sprite(dev_priv, pipe, sprite) {
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u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
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I915_STATE_WARN(val & SP_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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sprite_name(pipe, sprite), pipe_name(pipe));
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}
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} else if (INTEL_GEN(dev_priv) >= 7) {
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u32 val = I915_READ(SPRCTL(pipe));
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I915_STATE_WARN(val & SPRITE_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
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u32 val = I915_READ(DVSCNTR(pipe));
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I915_STATE_WARN(val & DVS_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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}
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for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
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assert_plane_disabled(plane);
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}
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static void assert_vblank_disabled(struct drm_crtc *crtc)
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@ -1918,9 +1849,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
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assert_planes_disabled(dev_priv, pipe);
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assert_cursor_disabled(dev_priv, pipe);
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assert_sprites_disabled(dev_priv, pipe);
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assert_planes_disabled(crtc);
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/*
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* A pipe without a PLL won't actually be able to drive bits from
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@ -1989,9 +1918,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
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* Make sure planes won't keep trying to pump pixels to us,
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* or we might hang the display.
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*/
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assert_planes_disabled(dev_priv, pipe);
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assert_cursor_disabled(dev_priv, pipe);
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assert_sprites_disabled(dev_priv, pipe);
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assert_planes_disabled(crtc);
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reg = PIPECONF(cpu_transcoder);
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val = I915_READ(reg);
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@ -2820,6 +2747,23 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
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crtc_state->active_planes);
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}
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static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
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struct intel_plane *plane)
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{
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struct intel_crtc_state *crtc_state =
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to_intel_crtc_state(crtc->base.state);
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struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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intel_set_plane_visible(crtc_state, plane_state, false);
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if (plane->id == PLANE_PRIMARY)
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intel_pre_disable_primary_noatomic(&crtc->base);
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trace_intel_disable_plane(&plane->base, crtc);
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plane->disable_plane(plane, crtc);
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}
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static void
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intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
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struct intel_initial_plane_config *plane_config)
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@ -2877,12 +2821,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
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* simplest solution is to just disable the primary plane now and
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* pretend the BIOS never had it enabled.
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*/
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intel_set_plane_visible(to_intel_crtc_state(crtc_state),
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to_intel_plane_state(plane_state),
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false);
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intel_pre_disable_primary_noatomic(&intel_crtc->base);
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trace_intel_disable_plane(primary, intel_crtc);
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intel_plane->disable_plane(intel_plane, intel_crtc);
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intel_plane_disable_noatomic(intel_crtc, intel_plane);
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return;
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@ -3385,6 +3324,31 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
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{
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struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
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enum intel_display_power_domain power_domain;
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enum plane plane = primary->plane;
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enum pipe pipe = primary->pipe;
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bool ret;
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/*
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* Not 100% correct for planes that can move between pipes,
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* but that's only the case for gen2-4 which don't have any
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* display power wells.
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*/
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static u32
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intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
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{
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@ -4866,7 +4830,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
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* a vblank wait.
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*/
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assert_plane_enabled(dev_priv, crtc->plane);
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assert_plane_enabled(to_intel_plane(crtc->base.primary));
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->pcu_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
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@ -4899,7 +4864,8 @@ void hsw_disable_ips(struct intel_crtc *crtc)
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if (!crtc->config->ips_enabled)
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return;
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assert_plane_enabled(dev_priv, crtc->plane);
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assert_plane_enabled(to_intel_plane(crtc->base.primary));
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->pcu_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
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@ -5899,6 +5865,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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enum intel_display_power_domain domain;
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struct intel_plane *plane;
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u64 domains;
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struct drm_atomic_state *state;
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struct intel_crtc_state *crtc_state;
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@ -5907,11 +5874,12 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
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if (!intel_crtc->active)
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return;
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if (crtc->primary->state->visible) {
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intel_pre_disable_primary_noatomic(crtc);
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for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
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const struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
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crtc->primary->state->visible = false;
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if (plane_state->base.visible)
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intel_plane_disable_noatomic(intel_crtc, plane);
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}
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state = drm_atomic_state_alloc(crtc->dev);
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@ -9477,6 +9445,23 @@ static void i845_disable_cursor(struct intel_plane *plane,
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i845_update_cursor(plane, NULL, NULL);
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}
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static bool i845_cursor_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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bool ret;
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power_domain = POWER_DOMAIN_PIPE(PIPE_A);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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@ -9670,6 +9655,28 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
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i9xx_update_cursor(plane, NULL, NULL);
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}
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static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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enum pipe pipe = plane->pipe;
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bool ret;
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/*
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* Not 100% correct for planes that can move between pipes,
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* but that's only the case for gen2-3 which don't have any
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* display power wells.
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*/
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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/* VESA 640x480x72Hz mode to set on the pipe */
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static const struct drm_display_mode load_detect_mode = {
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@ -13205,6 +13212,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = skl_update_plane;
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primary->disable_plane = skl_disable_plane;
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primary->get_hw_state = skl_plane_get_hw_state;
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} else if (INTEL_GEN(dev_priv) >= 9) {
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intel_primary_formats = skl_primary_formats;
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num_formats = ARRAY_SIZE(skl_primary_formats);
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@ -13215,6 +13223,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = skl_update_plane;
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primary->disable_plane = skl_disable_plane;
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primary->get_hw_state = skl_plane_get_hw_state;
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} else if (INTEL_GEN(dev_priv) >= 4) {
|
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intel_primary_formats = i965_primary_formats;
|
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num_formats = ARRAY_SIZE(i965_primary_formats);
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|
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@ -13222,6 +13231,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = i9xx_update_primary_plane;
|
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primary->disable_plane = i9xx_disable_primary_plane;
|
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primary->get_hw_state = i9xx_plane_get_hw_state;
|
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} else {
|
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intel_primary_formats = i8xx_primary_formats;
|
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num_formats = ARRAY_SIZE(i8xx_primary_formats);
|
||||
|
|
@ -13229,6 +13239,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
|
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|
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primary->update_plane = i9xx_update_primary_plane;
|
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primary->disable_plane = i9xx_disable_primary_plane;
|
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primary->get_hw_state = i9xx_plane_get_hw_state;
|
||||
}
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 9)
|
||||
|
|
@ -13318,10 +13329,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
|
|||
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
|
||||
cursor->update_plane = i845_update_cursor;
|
||||
cursor->disable_plane = i845_disable_cursor;
|
||||
cursor->get_hw_state = i845_cursor_get_hw_state;
|
||||
cursor->check_plane = i845_check_cursor;
|
||||
} else {
|
||||
cursor->update_plane = i9xx_update_cursor;
|
||||
cursor->disable_plane = i9xx_disable_cursor;
|
||||
cursor->get_hw_state = i9xx_cursor_get_hw_state;
|
||||
cursor->check_plane = i9xx_check_cursor;
|
||||
}
|
||||
|
||||
|
|
@ -14671,8 +14684,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
|
|||
DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
|
||||
pipe_name(pipe));
|
||||
|
||||
assert_plane_disabled(dev_priv, PLANE_A);
|
||||
assert_plane_disabled(dev_priv, PLANE_B);
|
||||
WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
|
||||
WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
|
||||
WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
|
||||
WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
|
||||
WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
|
||||
|
||||
I915_WRITE(PIPECONF(pipe), 0);
|
||||
POSTING_READ(PIPECONF(pipe));
|
||||
|
|
@ -14683,22 +14699,36 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
|
|||
POSTING_READ(DPLL(pipe));
|
||||
}
|
||||
|
||||
static bool
|
||||
intel_check_plane_mapping(struct intel_crtc *crtc)
|
||||
static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
|
||||
struct intel_plane *primary)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
u32 val;
|
||||
enum plane plane = primary->plane;
|
||||
u32 val = I915_READ(DSPCNTR(plane));
|
||||
|
||||
if (INTEL_INFO(dev_priv)->num_pipes == 1)
|
||||
return true;
|
||||
return (val & DISPLAY_PLANE_ENABLE) == 0 ||
|
||||
(val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
|
||||
}
|
||||
|
||||
val = I915_READ(DSPCNTR(!crtc->plane));
|
||||
static void
|
||||
intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
if ((val & DISPLAY_PLANE_ENABLE) &&
|
||||
(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
|
||||
return false;
|
||||
if (INTEL_GEN(dev_priv) >= 4)
|
||||
return;
|
||||
|
||||
return true;
|
||||
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
||||
struct intel_plane *plane =
|
||||
to_intel_plane(crtc->base.primary);
|
||||
|
||||
if (intel_plane_mapping_ok(crtc, plane))
|
||||
continue;
|
||||
|
||||
DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
|
||||
plane->base.name);
|
||||
intel_plane_disable_noatomic(crtc, plane);
|
||||
}
|
||||
}
|
||||
|
||||
static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
|
||||
|
|
@ -14754,33 +14784,15 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
|
|||
|
||||
/* Disable everything but the primary plane */
|
||||
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
||||
if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
|
||||
continue;
|
||||
const struct intel_plane_state *plane_state =
|
||||
to_intel_plane_state(plane->base.state);
|
||||
|
||||
trace_intel_disable_plane(&plane->base, crtc);
|
||||
plane->disable_plane(plane, crtc);
|
||||
if (plane_state->base.visible &&
|
||||
plane->base.type != DRM_PLANE_TYPE_PRIMARY)
|
||||
intel_plane_disable_noatomic(crtc, plane);
|
||||
}
|
||||
}
|
||||
|
||||
/* We need to sanitize the plane -> pipe mapping first because this will
|
||||
* disable the crtc (and hence change the state) if it is wrong. Note
|
||||
* that gen4+ has a fixed plane -> pipe mapping. */
|
||||
if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
|
||||
bool plane;
|
||||
|
||||
DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
|
||||
crtc->base.base.id, crtc->base.name);
|
||||
|
||||
/* Pipe has the wrong plane attached and the plane is active.
|
||||
* Temporarily change the plane mapping and disable everything
|
||||
* ... */
|
||||
plane = crtc->plane;
|
||||
crtc->base.primary->state->visible = true;
|
||||
crtc->plane = !plane;
|
||||
intel_crtc_disable_noatomic(&crtc->base, ctx);
|
||||
crtc->plane = plane;
|
||||
}
|
||||
|
||||
/* Adjust the state of the output pipe according to whether we
|
||||
* have active connectors/encoders. */
|
||||
if (crtc->active && !intel_crtc_has_encoders(crtc))
|
||||
|
|
@ -14885,24 +14897,21 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
|
|||
intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
|
||||
}
|
||||
|
||||
static bool primary_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
|
||||
return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
|
||||
}
|
||||
|
||||
/* FIXME read out full plane state for all planes */
|
||||
static void readout_plane_state(struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_plane *primary = to_intel_plane(crtc->base.primary);
|
||||
bool visible;
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
struct intel_crtc_state *crtc_state =
|
||||
to_intel_crtc_state(crtc->base.state);
|
||||
struct intel_plane *plane;
|
||||
|
||||
visible = crtc->active && primary_get_hw_state(primary);
|
||||
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
|
||||
struct intel_plane_state *plane_state =
|
||||
to_intel_plane_state(plane->base.state);
|
||||
bool visible = plane->get_hw_state(plane);
|
||||
|
||||
intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
|
||||
to_intel_plane_state(primary->base.state),
|
||||
visible);
|
||||
intel_set_plane_visible(crtc_state, plane_state, visible);
|
||||
}
|
||||
}
|
||||
|
||||
static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
||||
|
|
@ -15100,6 +15109,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
|
|||
/* HW state is read out, now we need to sanitize this mess. */
|
||||
get_encoder_power_domains(dev_priv);
|
||||
|
||||
intel_sanitize_plane_mapping(dev_priv);
|
||||
|
||||
for_each_intel_encoder(dev, encoder) {
|
||||
intel_sanitize_encoder(encoder);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -862,6 +862,7 @@ struct intel_plane {
|
|||
const struct intel_plane_state *plane_state);
|
||||
void (*disable_plane)(struct intel_plane *plane,
|
||||
struct intel_crtc *crtc);
|
||||
bool (*get_hw_state)(struct intel_plane *plane);
|
||||
int (*check_plane)(struct intel_plane *plane,
|
||||
struct intel_crtc_state *crtc_state,
|
||||
struct intel_plane_state *state);
|
||||
|
|
@ -1924,6 +1925,7 @@ void skl_update_plane(struct intel_plane *plane,
|
|||
const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state);
|
||||
void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
|
||||
bool skl_plane_get_hw_state(struct intel_plane *plane);
|
||||
|
||||
/* intel_tv.c */
|
||||
void intel_tv_init(struct drm_i915_private *dev_priv);
|
||||
|
|
|
|||
|
|
@ -329,6 +329,26 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
|||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
bool
|
||||
skl_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum plane_id plane_id = plane->id;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
chv_update_csc(struct intel_plane *plane, uint32_t format)
|
||||
{
|
||||
|
|
@ -506,6 +526,26 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
|||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static bool
|
||||
vlv_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum plane_id plane_id = plane->id;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
|
|
@ -646,6 +686,25 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
|||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static bool
|
||||
ivb_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
|
|
@ -777,6 +836,25 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
|||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static bool
|
||||
g4x_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
intel_check_sprite_plane(struct intel_plane *plane,
|
||||
struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -1232,6 +1310,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_plane->update_plane = skl_update_plane;
|
||||
intel_plane->disable_plane = skl_disable_plane;
|
||||
intel_plane->get_hw_state = skl_plane_get_hw_state;
|
||||
|
||||
plane_formats = skl_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
|
||||
|
|
@ -1242,6 +1321,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_plane->update_plane = skl_update_plane;
|
||||
intel_plane->disable_plane = skl_disable_plane;
|
||||
intel_plane->get_hw_state = skl_plane_get_hw_state;
|
||||
|
||||
plane_formats = skl_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
|
||||
|
|
@ -1252,6 +1332,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_plane->update_plane = vlv_update_plane;
|
||||
intel_plane->disable_plane = vlv_disable_plane;
|
||||
intel_plane->get_hw_state = vlv_plane_get_hw_state;
|
||||
|
||||
plane_formats = vlv_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
|
||||
|
|
@ -1267,6 +1348,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_plane->update_plane = ivb_update_plane;
|
||||
intel_plane->disable_plane = ivb_disable_plane;
|
||||
intel_plane->get_hw_state = ivb_plane_get_hw_state;
|
||||
|
||||
plane_formats = snb_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
||||
|
|
@ -1277,6 +1359,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
|||
|
||||
intel_plane->update_plane = g4x_update_plane;
|
||||
intel_plane->disable_plane = g4x_disable_plane;
|
||||
intel_plane->get_hw_state = g4x_plane_get_hw_state;
|
||||
|
||||
modifiers = i9xx_plane_format_modifiers;
|
||||
if (IS_GEN6(dev_priv)) {
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ int nv41_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
|||
int nv44_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int nv50_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int g84_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int mcp77_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int gf100_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int gk104_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
int gk20a_mmu_new(struct nvkm_device *, int, struct nvkm_mmu **);
|
||||
|
|
|
|||
|
|
@ -1447,11 +1447,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
|||
args.nv50.ro = 0;
|
||||
args.nv50.kind = mem->kind;
|
||||
args.nv50.comp = mem->comp;
|
||||
argc = sizeof(args.nv50);
|
||||
break;
|
||||
case NVIF_CLASS_MEM_GF100:
|
||||
args.gf100.version = 0;
|
||||
args.gf100.ro = 0;
|
||||
args.gf100.kind = mem->kind;
|
||||
argc = sizeof(args.gf100);
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
|
|
@ -1459,7 +1461,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
|||
}
|
||||
|
||||
ret = nvif_object_map_handle(&mem->mem.object,
|
||||
&argc, argc,
|
||||
&args, argc,
|
||||
&handle, &length);
|
||||
if (ret != 1)
|
||||
return ret ? ret : -EINVAL;
|
||||
|
|
|
|||
|
|
@ -1251,7 +1251,7 @@ nvaa_chipset = {
|
|||
.i2c = g94_i2c_new,
|
||||
.imem = nv50_instmem_new,
|
||||
.mc = g98_mc_new,
|
||||
.mmu = g84_mmu_new,
|
||||
.mmu = mcp77_mmu_new,
|
||||
.mxm = nv50_mxm_new,
|
||||
.pci = g94_pci_new,
|
||||
.therm = g84_therm_new,
|
||||
|
|
@ -1283,7 +1283,7 @@ nvac_chipset = {
|
|||
.i2c = g94_i2c_new,
|
||||
.imem = nv50_instmem_new,
|
||||
.mc = g98_mc_new,
|
||||
.mmu = g84_mmu_new,
|
||||
.mmu = mcp77_mmu_new,
|
||||
.mxm = nv50_mxm_new,
|
||||
.pci = g94_pci_new,
|
||||
.therm = g84_therm_new,
|
||||
|
|
|
|||
|
|
@ -73,7 +73,8 @@ static int
|
|||
nvkm_bar_fini(struct nvkm_subdev *subdev, bool suspend)
|
||||
{
|
||||
struct nvkm_bar *bar = nvkm_bar(subdev);
|
||||
bar->func->bar1.fini(bar);
|
||||
if (bar->func->bar1.fini)
|
||||
bar->func->bar1.fini(bar);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@ gk20a_bar_func = {
|
|||
.dtor = gf100_bar_dtor,
|
||||
.oneinit = gf100_bar_oneinit,
|
||||
.bar1.init = gf100_bar_bar1_init,
|
||||
.bar1.fini = gf100_bar_bar1_fini,
|
||||
.bar1.wait = gf100_bar_bar1_wait,
|
||||
.bar1.vmm = gf100_bar_bar1_vmm,
|
||||
.flush = g84_bar_flush,
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ nvkm-y += nvkm/subdev/mmu/nv41.o
|
|||
nvkm-y += nvkm/subdev/mmu/nv44.o
|
||||
nvkm-y += nvkm/subdev/mmu/nv50.o
|
||||
nvkm-y += nvkm/subdev/mmu/g84.o
|
||||
nvkm-y += nvkm/subdev/mmu/mcp77.o
|
||||
nvkm-y += nvkm/subdev/mmu/gf100.o
|
||||
nvkm-y += nvkm/subdev/mmu/gk104.o
|
||||
nvkm-y += nvkm/subdev/mmu/gk20a.o
|
||||
|
|
@ -22,6 +23,7 @@ nvkm-y += nvkm/subdev/mmu/vmmnv04.o
|
|||
nvkm-y += nvkm/subdev/mmu/vmmnv41.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmnv44.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmnv50.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmmcp77.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmgf100.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmgk104.o
|
||||
nvkm-y += nvkm/subdev/mmu/vmmgk20a.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2017 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "mem.h"
|
||||
#include "vmm.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
static const struct nvkm_mmu_func
|
||||
mcp77_mmu = {
|
||||
.dma_bits = 40,
|
||||
.mmu = {{ -1, -1, NVIF_CLASS_MMU_NV50}},
|
||||
.mem = {{ -1, 0, NVIF_CLASS_MEM_NV50}, nv50_mem_new, nv50_mem_map },
|
||||
.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV50}, mcp77_vmm_new, false, 0x0200 },
|
||||
.kind = nv50_mmu_kind,
|
||||
.kind_sys = true,
|
||||
};
|
||||
|
||||
int
|
||||
mcp77_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
|
||||
{
|
||||
return nvkm_mmu_new_(&mcp77_mmu, device, index, pmmu);
|
||||
}
|
||||
|
|
@ -95,6 +95,9 @@ struct nvkm_vmm_desc {
|
|||
const struct nvkm_vmm_desc_func *func;
|
||||
};
|
||||
|
||||
extern const struct nvkm_vmm_desc nv50_vmm_desc_12[];
|
||||
extern const struct nvkm_vmm_desc nv50_vmm_desc_16[];
|
||||
|
||||
extern const struct nvkm_vmm_desc gk104_vmm_desc_16_12[];
|
||||
extern const struct nvkm_vmm_desc gk104_vmm_desc_16_16[];
|
||||
extern const struct nvkm_vmm_desc gk104_vmm_desc_17_12[];
|
||||
|
|
@ -169,6 +172,11 @@ int nv04_vmm_new_(const struct nvkm_vmm_func *, struct nvkm_mmu *, u32,
|
|||
const char *, struct nvkm_vmm **);
|
||||
int nv04_vmm_valid(struct nvkm_vmm *, void *, u32, struct nvkm_vmm_map *);
|
||||
|
||||
int nv50_vmm_join(struct nvkm_vmm *, struct nvkm_memory *);
|
||||
void nv50_vmm_part(struct nvkm_vmm *, struct nvkm_memory *);
|
||||
int nv50_vmm_valid(struct nvkm_vmm *, void *, u32, struct nvkm_vmm_map *);
|
||||
void nv50_vmm_flush(struct nvkm_vmm *, int);
|
||||
|
||||
int gf100_vmm_new_(const struct nvkm_vmm_func *, const struct nvkm_vmm_func *,
|
||||
struct nvkm_mmu *, u64, u64, void *, u32,
|
||||
struct lock_class_key *, const char *, struct nvkm_vmm **);
|
||||
|
|
@ -200,6 +208,8 @@ int nv44_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
|
|||
struct lock_class_key *, const char *, struct nvkm_vmm **);
|
||||
int nv50_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
|
||||
struct lock_class_key *, const char *, struct nvkm_vmm **);
|
||||
int mcp77_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
|
||||
struct lock_class_key *, const char *, struct nvkm_vmm **);
|
||||
int g84_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
|
||||
struct lock_class_key *, const char *, struct nvkm_vmm **);
|
||||
int gf100_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright 2017 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "vmm.h"
|
||||
|
||||
static const struct nvkm_vmm_func
|
||||
mcp77_vmm = {
|
||||
.join = nv50_vmm_join,
|
||||
.part = nv50_vmm_part,
|
||||
.valid = nv50_vmm_valid,
|
||||
.flush = nv50_vmm_flush,
|
||||
.page_block = 1 << 29,
|
||||
.page = {
|
||||
{ 16, &nv50_vmm_desc_16[0], NVKM_VMM_PAGE_xVxx },
|
||||
{ 12, &nv50_vmm_desc_12[0], NVKM_VMM_PAGE_xVHx },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
mcp77_vmm_new(struct nvkm_mmu *mmu, u64 addr, u64 size, void *argv, u32 argc,
|
||||
struct lock_class_key *key, const char *name,
|
||||
struct nvkm_vmm **pvmm)
|
||||
{
|
||||
return nv04_vmm_new_(&mcp77_vmm, mmu, 0, addr, size,
|
||||
argv, argc, key, name, pvmm);
|
||||
}
|
||||
|
|
@ -32,7 +32,7 @@ static inline void
|
|||
nv50_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
|
||||
u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
|
||||
{
|
||||
u64 next = addr | map->type, data;
|
||||
u64 next = addr + map->type, data;
|
||||
u32 pten;
|
||||
int log2blk;
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ nv50_vmm_pgt_dma(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt,
|
|||
VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
|
||||
nvkm_kmap(pt->memory);
|
||||
while (ptes--) {
|
||||
const u64 data = *map->dma++ | map->type;
|
||||
const u64 data = *map->dma++ + map->type;
|
||||
VMM_WO064(pt, vmm, ptei++ * 8, data);
|
||||
map->type += map->ctag;
|
||||
}
|
||||
|
|
@ -163,21 +163,21 @@ nv50_vmm_pgd = {
|
|||
.pde = nv50_vmm_pgd_pde,
|
||||
};
|
||||
|
||||
static const struct nvkm_vmm_desc
|
||||
const struct nvkm_vmm_desc
|
||||
nv50_vmm_desc_12[] = {
|
||||
{ PGT, 17, 8, 0x1000, &nv50_vmm_pgt },
|
||||
{ PGD, 11, 0, 0x0000, &nv50_vmm_pgd },
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct nvkm_vmm_desc
|
||||
const struct nvkm_vmm_desc
|
||||
nv50_vmm_desc_16[] = {
|
||||
{ PGT, 13, 8, 0x1000, &nv50_vmm_pgt },
|
||||
{ PGD, 11, 0, 0x0000, &nv50_vmm_pgd },
|
||||
{}
|
||||
};
|
||||
|
||||
static void
|
||||
void
|
||||
nv50_vmm_flush(struct nvkm_vmm *vmm, int level)
|
||||
{
|
||||
struct nvkm_subdev *subdev = &vmm->mmu->subdev;
|
||||
|
|
@ -223,7 +223,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level)
|
|||
mutex_unlock(&subdev->mutex);
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
nv50_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
|
||||
struct nvkm_vmm_map *map)
|
||||
{
|
||||
|
|
@ -321,7 +321,7 @@ nv50_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
void
|
||||
nv50_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
|
||||
{
|
||||
struct nvkm_vmm_join *join;
|
||||
|
|
@ -335,7 +335,7 @@ nv50_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
|
|||
}
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
nv50_vmm_join(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
|
||||
{
|
||||
const u32 pd_offset = vmm->mmu->func->vmm.pd_offset;
|
||||
|
|
|
|||
|
|
@ -102,10 +102,13 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (abs(rate - rounded / i) <
|
||||
abs(rate - best_parent / best_div)) {
|
||||
if (!best_parent ||
|
||||
abs(rate - rounded / i / j) <
|
||||
abs(rate - best_parent / best_half /
|
||||
best_div)) {
|
||||
best_parent = rounded;
|
||||
best_div = i;
|
||||
best_half = i;
|
||||
best_div = j;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1863,7 +1863,7 @@ u32 vmw_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
|
|||
*/
|
||||
int vmw_enable_vblank(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
return -ENOSYS;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -266,8 +266,8 @@ static const struct drm_connector_funcs vmw_legacy_connector_funcs = {
|
|||
.set_property = vmw_du_connector_set_property,
|
||||
.destroy = vmw_ldu_connector_destroy,
|
||||
.reset = vmw_du_connector_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
||||
.atomic_duplicate_state = vmw_du_connector_duplicate_state,
|
||||
.atomic_destroy_state = vmw_du_connector_destroy_state,
|
||||
.atomic_set_property = vmw_du_connector_atomic_set_property,
|
||||
.atomic_get_property = vmw_du_connector_atomic_get_property,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -420,8 +420,8 @@ static const struct drm_connector_funcs vmw_sou_connector_funcs = {
|
|||
.set_property = vmw_du_connector_set_property,
|
||||
.destroy = vmw_sou_connector_destroy,
|
||||
.reset = vmw_du_connector_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
||||
.atomic_duplicate_state = vmw_du_connector_duplicate_state,
|
||||
.atomic_destroy_state = vmw_du_connector_destroy_state,
|
||||
.atomic_set_property = vmw_du_connector_atomic_set_property,
|
||||
.atomic_get_property = vmw_du_connector_atomic_get_property,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue