openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/nouveau/device: include core/device.h automatically for subdevs/engines 

Pretty much every subdev/engine is going to need access to nvkm_device
shortly to touch registers and/or output messages.

The odd placement of the includes is necessary to work around some
inter-dependencies that currently exist.  This will be fixed later.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:06 +10:00
parent 6d0d40e7a5
commit 9ace404b10
78 changed files with 65 additions and 159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -3,6 +3,66 @@
#include <core/engine.h>
#include <core/event.h>
enum nvkm_devidx {
NVDEV_ENGINE_DEVICE,
NVDEV_SUBDEV_VBIOS,
/* All subdevs from DEVINIT to DEVINIT_LAST will be created before
* *any* of them are initialised. This subdev category is used
* for any subdevs that the VBIOS init table parsing may call out
* to during POST.
*/
NVDEV_SUBDEV_DEVINIT,
NVDEV_SUBDEV_IBUS,
NVDEV_SUBDEV_GPIO,
NVDEV_SUBDEV_I2C,
NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
/* This grouping of subdevs are initialised right after they've
* been created, and are allowed to assume any subdevs in the
* list above them exist and have been initialised.
*/
NVDEV_SUBDEV_FUSE,
NVDEV_SUBDEV_MXM,
NVDEV_SUBDEV_MC,
NVDEV_SUBDEV_BUS,
NVDEV_SUBDEV_TIMER,
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTC,
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_MMU,
NVDEV_SUBDEV_BAR,
NVDEV_SUBDEV_PMU,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLK,
NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_IFB,
NVDEV_ENGINE_FIFO,
NVDEV_ENGINE_SW,
NVDEV_ENGINE_GR,
NVDEV_ENGINE_MPEG,
NVDEV_ENGINE_ME,
NVDEV_ENGINE_VP,
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_MSPPP,
NVDEV_ENGINE_CE0,
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_MSENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
NVDEV_ENGINE_MSPDEC,
NVDEV_SUBDEV_NR,
};
struct nvkm_device {
struct nvkm_engine engine;
struct list_head head;

62
drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h
View File

@ -1,62 +0,0 @@
#ifndef __NVKM_DEVIDX_H__
#define __NVKM_DEVIDX_H__
enum nvkm_devidx {
NVDEV_ENGINE_DEVICE,
NVDEV_SUBDEV_VBIOS,
/* All subdevs from DEVINIT to DEVINIT_LAST will be created before
* *any* of them are initialised. This subdev category is used
* for any subdevs that the VBIOS init table parsing may call out
* to during POST.
*/
NVDEV_SUBDEV_DEVINIT,
NVDEV_SUBDEV_IBUS,
NVDEV_SUBDEV_GPIO,
NVDEV_SUBDEV_I2C,
NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
/* This grouping of subdevs are initialised right after they've
* been created, and are allowed to assume any subdevs in the
* list above them exist and have been initialised.
*/
NVDEV_SUBDEV_FUSE,
NVDEV_SUBDEV_MXM,
NVDEV_SUBDEV_MC,
NVDEV_SUBDEV_BUS,
NVDEV_SUBDEV_TIMER,
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTC,
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_MMU,
NVDEV_SUBDEV_BAR,
NVDEV_SUBDEV_PMU,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLK,
NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_IFB,
NVDEV_ENGINE_FIFO,
NVDEV_ENGINE_SW,
NVDEV_ENGINE_GR,
NVDEV_ENGINE_MPEG,
NVDEV_ENGINE_ME,
NVDEV_ENGINE_VP,
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_MSPPP,
NVDEV_ENGINE_CE0,
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_MSENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,
NVDEV_ENGINE_SEC,
NVDEV_ENGINE_MSPDEC,
NVDEV_SUBDEV_NR,
};
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View File

@ -53,4 +53,6 @@ int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *,
#define _nvkm_engine_dtor _nvkm_subdev_dtor
#define _nvkm_engine_init _nvkm_subdev_init
#define _nvkm_engine_fini _nvkm_subdev_fini
#include <core/device.h>
#endif

3
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
View File

@ -1,7 +1,6 @@
#ifndef __NVKM_SUBDEV_H__
#define __NVKM_SUBDEV_H__
#include <core/object.h>
#include <core/devidx.h>
#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub))
#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
@ -119,4 +118,6 @@ nv_mask(void *obj, u32 addr, u32 mask, u32 data)
nv_wr32(obj, addr, (temp & ~mask) | data);
return temp;
}
#include <core/engine.h>
#endif

4
drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h
View File

@ -1,7 +1,6 @@
#ifndef __NOUVEAU_VGA_H__
#define __NOUVEAU_VGA_H__
#include <core/os.h>
#include <core/subdev.h>
/* access to various legacy io ports */
u8 nv_rdport(void *obj, int head, u16 port);
@ -26,5 +25,4 @@ void nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value);
bool nv_lockvgac(void *obj, bool lock);
u8 nv_rdvgaowner(void *obj);
void nv_wrvgaowner(void *obj, u8);
#endif

1
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
View File

@ -27,7 +27,6 @@
#include "fuc/gt215.fuc3.h"
#include <core/client.h>
#include <core/device.h>
#include <core/enum.h>
struct gt215_ce_priv {

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c
View File

@ -24,7 +24,6 @@
#include "priv.h"
#include <core/client.h>
#include <core/device.h>
#include <nvif/class.h>
#include <nvif/unpack.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View File

@ -26,7 +26,6 @@
#include "outpdp.h"
#include <core/client.h>
#include <core/device.h>
#include <core/engctx.h>
#include <core/enum.h>
#include <core/handle.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
View File

@ -24,7 +24,6 @@
#include "nv50.h"
#include "outpdp.h"
#include <core/device.h>
#include <subdev/timer.h>
static inline u32

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c
View File

@ -23,8 +23,6 @@
*/
#include <subdev/vga.h>
#include <core/device.h>
u8
nv_rdport(void *obj, int head, u16 port)
{

1
drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
View File

@ -24,7 +24,6 @@
#include "priv.h"
#include <core/client.h>
#include <core/device.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
View File

@ -21,7 +21,6 @@
*/
#include <engine/falcon.h>
#include <core/device.h>
#include <subdev/timer.h>
void

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View File

@ -24,7 +24,6 @@
#include <engine/fifo.h>
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <core/notify.h>
#include <engine/dmaobj.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -24,7 +24,6 @@
#include "nv04.h"
#include <core/client.h>
#include <core/device.h>
#include <core/engctx.h>
#include <core/handle.h>
#include <core/ramht.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -24,7 +24,6 @@
#include "nv04.h"
#include <core/client.h>
#include <core/device.h>
#include <core/engctx.h>
#include <core/ramht.h>
#include <subdev/fb.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
View File

@ -111,7 +111,6 @@
#include "ctxnv40.h"
#include "nv40.h"
#include <core/device.h>
/* TODO:
* - get vs count from 0x1540

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
View File

@ -107,7 +107,6 @@
#include "ctxnv40.h"
#include <core/device.h>
#include <subdev/fb.h>
#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -26,7 +26,6 @@
#include "fuc/os.h"
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <core/option.h>
#include <engine/fifo.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View File

@ -25,7 +25,6 @@
#include "regs.h"
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/instmem.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View File

@ -25,7 +25,6 @@
#include "regs.h"
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/fb.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
View File

@ -2,7 +2,6 @@
#include "regs.h"
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/fb.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
View File

@ -1,7 +1,6 @@
#include "nv20.h"
#include "regs.h"
#include <core/device.h>
#include <engine/fifo.h>
#include <subdev/fb.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
View File

@ -2,7 +2,6 @@
#define __NV40_GR_H__
#include <engine/gr.h>
#include <core/device.h>
struct nvkm_gpuobj;
/* returns 1 if device is one of the nv4x using the 0x4497 object class,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
View File

@ -24,7 +24,6 @@
#include "nv50.h"
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
View File

@ -24,7 +24,6 @@
#include "priv.h"
#include <core/client.h>
#include <core/device.h>
#include <core/option.h>
#include <nvif/class.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
View File

@ -23,7 +23,6 @@
*/
#include "nv50.h"
#include <core/device.h>
#include <core/handle.h>
#include <core/namedb.h>
#include <engine/disp.h>

1
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
View File

@ -20,7 +20,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <engine/xtensa.h>
#include <core/device.h>
#include <core/engctx.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
View File

@ -24,8 +24,6 @@
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <core/device.h>
u16
dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{

1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
View File

@ -31,7 +31,6 @@
#include <subdev/bios/init.h>
#include <subdev/bios/ramcfg.h>
#include <core/device.h>
#include <subdev/devinit.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
View File

@ -25,8 +25,6 @@
#include <subdev/bios/bit.h>
#include <subdev/bios/perf.h>
#include <core/device.h>
u16
nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)

1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
View File

@ -27,7 +27,6 @@
#include <subdev/bios/pll.h>
#include <subdev/vga.h>
#include <core/device.h>
struct pll_mapping {
u8 type;

1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/image.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
View File

@ -22,8 +22,6 @@
*/
#include "priv.h"
#include <core/device.h>
#if defined(CONFIG_ACPI) && defined(CONFIG_X86)
int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
bool nouveau_acpi_rom_supported(struct pci_dev *pdev);

1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
View File

@ -22,7 +22,6 @@
*/
#include "priv.h"
#include <core/device.h>
#if defined(__powerpc__)
struct priv {

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
View File

@ -22,8 +22,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct priv {
struct pci_dev *pdev;
void __iomem *rom;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
View File

@ -22,8 +22,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct priv {
struct nvkm_bios *bios;
u32 bar0;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
View File

@ -22,8 +22,6 @@
*/
#include "priv.h"
#include <core/device.h>
static u32
prom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
{

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
View File

@ -25,8 +25,6 @@
#include <subdev/bios/bit.h>
#include <subdev/bios/therm.h>
#include <core/device.h>
static u16
therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt)
{

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -30,7 +30,6 @@
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <core/device.h>
#include <core/option.h>
/******************************************************************************

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
View File

@ -24,7 +24,6 @@
#include <subdev/clk.h>
#include "pll.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
View File

@ -24,7 +24,6 @@
#include <subdev/clk.h>
#include "pll.h"
#include <core/device.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
View File

@ -25,8 +25,6 @@
#include <subdev/clk.h>
#include <subdev/timer.h>
#include <core/device.h>
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
View File

@ -25,7 +25,6 @@
#include "gt215.h"
#include "pll.h"
#include <core/device.h>
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
View File

@ -24,7 +24,6 @@
#include "gt215.h"
#include "pll.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
View File

@ -24,7 +24,6 @@
#include <subdev/clk.h>
#include "pll.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
View File

@ -25,7 +25,6 @@
#include "pll.h"
#include "seq.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/vga.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h
View File

@ -23,7 +23,6 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <core/device.h>
#include <subdev/fb/regsnv04.h>
#define NV04_PFB_DEBUG_0 0x00100080

2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
View File

@ -23,8 +23,6 @@
*/
#include "gf100.h"
#include <core/device.h>
extern const u8 gf100_pte_storage_type_map[256];
bool

2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
View File

@ -25,8 +25,6 @@
*/
#include "nv04.h"
#include <core/device.h>
void
nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nvkm_fb_tile *tile)

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
View File

@ -24,7 +24,6 @@
#include "nv50.h"
#include <core/client.h>
#include <core/device.h>
#include <core/engctx.h>
#include <core/enum.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
View File

@ -24,7 +24,6 @@
#include "gf100.h"
#include "ramfuc.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
View File

@ -24,7 +24,6 @@
#include "ramfuc.h"
#include "gf100.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/init.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
View File

@ -26,7 +26,6 @@
#include "ramfuc.h"
#include "nv50.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/M0205.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
View File

@ -23,8 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
static int
nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
View File

@ -23,7 +23,6 @@
*/
#include "nv40.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/init.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
View File

@ -24,7 +24,6 @@
#include "nv50.h"
#include "ramseq.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/perf.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/notify.h>
static int

1
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
View File

@ -24,7 +24,6 @@
#include "priv.h"
#include "pad.h"
#include <core/device.h>
#include <core/notify.h>
#include <core/option.h>
#include <subdev/bios.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
View File

@ -40,7 +40,6 @@
#include <subdev/fb.h>
#include <core/mm.h>
#include <core/device.h>
#ifdef __KERNEL__
#include <linux/dma-attrs.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/option.h>
static inline void

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
View File

@ -23,8 +23,6 @@
*/
#include "nv04.h"
#include <core/device.h>
const struct nvkm_mc_intr
nv50_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */

1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
View File

@ -23,7 +23,6 @@
*/
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h>
#define NV04_PDMA_SIZE (128 * 1024 * 1024)

1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
View File

@ -23,7 +23,6 @@
*/
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h>
#include <core/option.h>
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
View File

@ -23,7 +23,6 @@
*/
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h>
#include <core/option.h>
#include <subdev/timer.h>

1
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
View File

@ -23,7 +23,6 @@
*/
#include "mxms.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/mxm.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
View File

@ -2,8 +2,6 @@
#define __NVKM_PMU_MEMX_H__
#include "priv.h"
#include <core/device.h>
struct nvkm_memx {
struct nvkm_pmu *pmu;
u32 base;

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
View File

@ -23,8 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
static int
nvkm_therm_update_trip(struct nvkm_therm *therm)
{

1
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
View File

@ -24,7 +24,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/option.h>
#include <subdev/bios.h>
#include <subdev/bios/fan.h>

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c
View File

@ -23,8 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct gf110_therm_priv {
struct nvkm_therm_priv base;
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c
View File

@ -23,8 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct gm107_therm_priv {
struct nvkm_therm_priv base;
};

1
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c
View File

@ -23,7 +23,6 @@
*/
#include "priv.h"
#include <core/device.h>
#include <subdev/gpio.h>
struct gt215_therm_priv {

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c
View File

@ -24,8 +24,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct nv40_therm_priv {
struct nvkm_therm_priv base;
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c
View File

@ -24,8 +24,6 @@
*/
#include "priv.h"
#include <core/device.h>
struct nv50_therm_priv {
struct nvkm_therm_priv base;
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
View File

@ -23,8 +23,6 @@
*/
#include "nv04.h"
#include <core/device.h>
static u64
nv04_timer_read(struct nvkm_timer *ptimer)
{