mirror of https://gitee.com/openkylin/linux.git
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
[ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32] [ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ] [ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic] [ben.dooks@codethink.co.uk: move mpic per-cpu register base ] [ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Yehuda Yitschak <yehuday@marvell.com> Tested-by: Lior Amsalem <alior@marvell.com>
This commit is contained in:
Thomas Petazzoni
Arnd Bergmann
parent
31af49db7b
commit
9ae6f740b4
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@ -0,0 +1,42 @@
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/*
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* Device Tree file for Marvell Armada 370 evaluation board
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* (DB-88F6710-BP-DDR3)
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "armada-370.dtsi"
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/ {
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model = "Marvell Armada 370 Evaluation Board";
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compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; /* 512 MB */
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};
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soc {
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serial@d0012000 {
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clock-frequency = <200000000>;
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status = "okay";
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};
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timer@d0020300 {
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clock-frequency = <600000000>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,68 @@
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/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Armada 370 and XP SoC";
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compatible = "marvell,armada_370_xp";
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cpus {
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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};
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};
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mpic: interrupt-controller@d0020000 {
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compatible = "marvell,mpic";
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&mpic>;
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ranges;
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serial@d0012000 {
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compatible = "ns16550";
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reg = <0xd0012000 0x100>;
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reg-shift = <2>;
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interrupts = <41>;
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status = "disabled";
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};
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serial@d0012100 {
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compatible = "ns16550";
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reg = <0xd0012100 0x100>;
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reg-shift = <2>;
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interrupts = <42>;
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status = "disabled";
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};
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timer@d0020300 {
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compatible = "marvell,armada-370-xp-timer";
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reg = <0xd0020300 0x30>;
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interrupts = <37>, <38>, <39>, <40>;
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};
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};
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};
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@ -0,0 +1,35 @@
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/*
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* Device Tree Include file for Marvell Armada 370 family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada 370 family SoC";
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compatible = "marvell,armada370", "marvell,armada-370-xp";
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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};
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soc {
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x100>;
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};
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};
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};
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@ -0,0 +1,50 @@
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/*
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* Device Tree file for Marvell Armada XP evaluation board
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* (DB-78460-BP)
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "armada-xp.dtsi"
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/ {
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model = "Marvell Armada XP Evaluation Board";
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compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>; /* 2 GB */
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};
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soc {
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serial@d0012000 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@d0012100 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@d0012200 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@d0012300 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,55 @@
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/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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};
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soc {
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serial@d0012200 {
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compatible = "ns16550";
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reg = <0xd0012200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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status = "disabled";
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};
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serial@d0012300 {
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compatible = "ns16550";
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reg = <0xd0012300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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status = "disabled";
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};
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timer@d0020300 {
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marvell,timer-25Mhz;
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};
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x500>;
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};
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};
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};
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@ -2,6 +2,15 @@ if ARCH_MVEBU
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menu "Marvell SOC with device tree"
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config MACH_ARMADA_370_XP
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bool "Marvell Armada 370 and Aramada XP boards"
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select ARMADA_370_XP_TIMER
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select CPU_V7
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help
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Say 'Y' here if you want your kernel to support boards based on
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Marvell Armada 370 or Armada XP with device tree.
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endmenu
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endif
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@ -1 +1,2 @@
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obj-y += system-controller.o
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obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
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/*
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* Device Tree support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/time-armada-370-xp.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/armada-370-xp.h>
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#include "common.h"
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static struct map_desc armada_370_xp_io_desc[] __initdata = {
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{
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.virtual = ARMADA_370_XP_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
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.length = ARMADA_370_XP_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init armada_370_xp_map_io(void)
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{
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iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
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}
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struct sys_timer armada_370_xp_timer = {
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.init = armada_370_xp_timer_init,
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};
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static void __init armada_370_xp_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char * const armada_370_xp_dt_board_dt_compat[] = {
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"marvell,a370-db",
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"marvell,axp-db",
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NULL,
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};
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DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
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.init_machine = armada_370_xp_dt_init,
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.map_io = armada_370_xp_map_io,
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.init_irq = armada_370_xp_init_irq,
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.handle_irq = armada_370_xp_handle_irq,
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.timer = &armada_370_xp_timer,
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.restart = mvebu_restart,
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.dt_compat = armada_370_xp_dt_board_dt_compat,
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MACHINE_END
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@ -17,4 +17,7 @@
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void mvebu_restart(char mode, const char *cmd);
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void armada_370_xp_init_irq(void);
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void armada_370_xp_handle_irq(struct pt_regs *regs);
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#endif
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@ -0,0 +1,22 @@
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/*
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* Generic definitions for Marvell Armada_370_XP SoCs
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_ARMADA_370_XP_H
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#define __MACH_ARMADA_370_XP_H
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#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
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#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
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#define ARMADA_370_XP_REGS_SIZE SZ_1M
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#endif /* __MACH_ARMADA_370_XP_H */
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/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_370_XP_NR_IRQS (115)
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static struct irq_chip armada_370_xp_irq_chip = {
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.name = "armada_370_xp_irq",
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.irq_mask = armada_370_xp_irq_mask,
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.irq_mask_ack = armada_370_xp_irq_mask,
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.irq_unmask = armada_370_xp_irq_unmask,
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};
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static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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armada_370_xp_irq_mask(irq_get_irq_data(virq));
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_level_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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.map = armada_370_xp_mpic_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init armada_370_xp_mpic_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
main_int_base = of_iomap(node, 0);
|
||||
per_cpu_int_base = of_iomap(node, 1);
|
||||
|
||||
BUG_ON(!main_int_base);
|
||||
BUG_ON(!per_cpu_int_base);
|
||||
|
||||
armada_370_xp_mpic_domain =
|
||||
irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
|
||||
&armada_370_xp_mpic_irq_ops, NULL);
|
||||
|
||||
if (!armada_370_xp_mpic_domain)
|
||||
panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
|
||||
|
||||
irq_set_default_host(armada_370_xp_mpic_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
|
||||
*regs)
|
||||
{
|
||||
u32 irqstat, irqnr;
|
||||
|
||||
do {
|
||||
irqstat = readl_relaxed(per_cpu_int_base +
|
||||
ARMADA_370_XP_CPU_INTACK_OFFS);
|
||||
irqnr = irqstat & 0x3FF;
|
||||
|
||||
if (irqnr < 1023) {
|
||||
irqnr =
|
||||
irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
|
||||
handle_IRQ(irqnr, regs);
|
||||
continue;
|
||||
}
|
||||
|
||||
break;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static const struct of_device_id mpic_of_match[] __initconst = {
|
||||
{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
|
||||
{},
|
||||
};
|
||||
|
||||
void __init armada_370_xp_init_irq(void)
|
||||
{
|
||||
of_irq_init(mpic_of_match);
|
||||
}
|
||||
Loading…
Reference in New Issue