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MIPS: Alchemy: remove no longer used au1xxx_ide.h header
Since the only user of this header (au1xxx-ide IDE host driver) is now gone it can also be removed. Acked-by: Paul Burton <paulburton@kernel.org> Acked-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Thomas Bogendoerfer
parent
823b30fe22
commit
9b2954b2ed
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/*
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* include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
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*
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* BRIEF MODULE DESCRIPTION
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* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
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*
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* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any later
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* version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
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* Interface and Linux Device Driver" Application Note.
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*/
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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#define DMA_WAIT_TIMEOUT 100
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#define NUM_DESCRIPTORS PRD_ENTRIES
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#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
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#define NUM_DESCRIPTORS 2
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#endif
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#ifndef AU1XXX_ATA_RQSIZE
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#define AU1XXX_ATA_RQSIZE 128
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#endif
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/* Disable Burstable-Support for DBDMA */
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#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
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#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
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#endif
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typedef struct {
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u32 tx_dev_id, rx_dev_id, target_dev_id;
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u32 tx_chan, rx_chan;
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void *tx_desc_head, *rx_desc_head;
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ide_hwif_t *hwif;
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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ide_drive_t *drive;
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struct dbdma_cmd *dma_table_cpu;
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dma_addr_t dma_table_dma;
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#endif
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int irq;
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u32 regbase;
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int ddma_id;
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} _auide_hwif;
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/******************************************************************************/
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/* PIO Mode timing calculation : */
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/* */
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/* Static Bus Spec ATA Spec */
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/* Tcsoe = t1 */
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/* Toecs = t9 */
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/* Twcs = t9 */
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/* Tcsh = t2i | t2 */
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/* Tcsoff = t2i | t2 */
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/* Twp = t2 */
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/* Tcsw = t1 */
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/* Tpm = 0 */
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/* Ta = t1+t2 */
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/******************************************************************************/
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#define TCSOE_MASK (0x07 << 29)
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#define TOECS_MASK (0x07 << 26)
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#define TWCS_MASK (0x07 << 28)
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#define TCSH_MASK (0x0F << 24)
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#define TCSOFF_MASK (0x07 << 20)
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#define TWP_MASK (0x3F << 14)
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#define TCSW_MASK (0x0F << 10)
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#define TPM_MASK (0x0F << 6)
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#define TA_MASK (0x3F << 0)
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#define TS_MASK (1 << 8)
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/* Timing parameters PIO mode 0 */
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#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
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#define SBC_IDE_PIO0_TOECS (0x01 << 26)
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#define SBC_IDE_PIO0_TWCS (0x02 << 28)
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#define SBC_IDE_PIO0_TCSH (0x08 << 24)
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#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
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#define SBC_IDE_PIO0_TWP (0x10 << 14)
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#define SBC_IDE_PIO0_TCSW (0x04 << 10)
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#define SBC_IDE_PIO0_TPM (0x00 << 6)
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#define SBC_IDE_PIO0_TA (0x15 << 0)
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/* Timing parameters PIO mode 1 */
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#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
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#define SBC_IDE_PIO1_TOECS (0x01 << 26)
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#define SBC_IDE_PIO1_TWCS (0x01 << 28)
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#define SBC_IDE_PIO1_TCSH (0x06 << 24)
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#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
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#define SBC_IDE_PIO1_TWP (0x08 << 14)
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#define SBC_IDE_PIO1_TCSW (0x03 << 10)
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#define SBC_IDE_PIO1_TPM (0x00 << 6)
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#define SBC_IDE_PIO1_TA (0x0B << 0)
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/* Timing parameters PIO mode 2 */
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#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
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#define SBC_IDE_PIO2_TOECS (0x01 << 26)
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#define SBC_IDE_PIO2_TWCS (0x01 << 28)
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#define SBC_IDE_PIO2_TCSH (0x07 << 24)
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#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
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#define SBC_IDE_PIO2_TWP (0x1F << 14)
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#define SBC_IDE_PIO2_TCSW (0x05 << 10)
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#define SBC_IDE_PIO2_TPM (0x00 << 6)
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#define SBC_IDE_PIO2_TA (0x22 << 0)
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/* Timing parameters PIO mode 3 */
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#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
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#define SBC_IDE_PIO3_TOECS (0x01 << 26)
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#define SBC_IDE_PIO3_TWCS (0x01 << 28)
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#define SBC_IDE_PIO3_TCSH (0x0D << 24)
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#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
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#define SBC_IDE_PIO3_TWP (0x15 << 14)
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#define SBC_IDE_PIO3_TCSW (0x05 << 10)
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#define SBC_IDE_PIO3_TPM (0x00 << 6)
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#define SBC_IDE_PIO3_TA (0x1A << 0)
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/* Timing parameters PIO mode 4 */
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#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
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#define SBC_IDE_PIO4_TOECS (0x01 << 26)
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#define SBC_IDE_PIO4_TWCS (0x01 << 28)
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#define SBC_IDE_PIO4_TCSH (0x04 << 24)
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#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
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#define SBC_IDE_PIO4_TWP (0x0D << 14)
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#define SBC_IDE_PIO4_TCSW (0x03 << 10)
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#define SBC_IDE_PIO4_TPM (0x00 << 6)
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#define SBC_IDE_PIO4_TA (0x12 << 0)
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/* Timing parameters MDMA mode 0 */
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#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
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#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
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#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
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#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
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#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
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#define SBC_IDE_MDMA0_TWP (0x0C << 14)
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#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
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#define SBC_IDE_MDMA0_TPM (0x00 << 6)
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#define SBC_IDE_MDMA0_TA (0x0F << 0)
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/* Timing parameters MDMA mode 1 */
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#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
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#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
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#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
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#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
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#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
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#define SBC_IDE_MDMA1_TWP (0x0F << 14)
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#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
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#define SBC_IDE_MDMA1_TPM (0x00 << 6)
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#define SBC_IDE_MDMA1_TA (0x15 << 0)
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/* Timing parameters MDMA mode 2 */
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#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
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#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
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#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
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#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
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#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
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#define SBC_IDE_MDMA2_TWP (0x0D << 14)
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#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
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#define SBC_IDE_MDMA2_TPM (0x00 << 6)
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#define SBC_IDE_MDMA2_TA (0x12 << 0)
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#define SBC_IDE_TIMING(mode) \
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(SBC_IDE_##mode##_TWCS | \
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SBC_IDE_##mode##_TCSH | \
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SBC_IDE_##mode##_TCSOFF | \
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SBC_IDE_##mode##_TWP | \
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SBC_IDE_##mode##_TCSW | \
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SBC_IDE_##mode##_TPM | \
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SBC_IDE_##mode##_TA)
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