mirror of https://gitee.com/openkylin/linux.git
drm/i915: Only wait for required lanes in vlv_wait_port_ready()
Currently vlv_wait_port_ready() waits for all four lanes on the appropriate channel. This no longer works on CHV when the unused lanes may be power gated. So pass in a mask of lanes that the caller is expecting to be ready. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1844,7 +1844,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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}
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void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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struct intel_digital_port *dport)
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struct intel_digital_port *dport,
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unsigned int expected_mask)
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{
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u32 port_mask;
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int dpll_reg;
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@ -1857,6 +1858,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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case PORT_C:
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port_mask = DPLL_PORTC_READY_MASK;
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dpll_reg = DPLL(0);
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expected_mask <<= 4;
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break;
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case PORT_D:
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port_mask = DPLL_PORTD_READY_MASK;
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@ -1866,9 +1868,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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BUG();
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}
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if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
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WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
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port_name(dport->port), I915_READ(dpll_reg));
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if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
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WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
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port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
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}
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static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
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@ -2497,6 +2497,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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uint32_t dp_reg = I915_READ(intel_dp->output_reg);
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unsigned int lane_mask = 0x0;
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if (WARN_ON(dp_reg & DP_PORT_EN))
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return;
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@ -2515,7 +2516,8 @@ static void intel_enable_dp(struct intel_encoder *encoder)
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pps_unlock(intel_dp);
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if (IS_VALLEYVIEW(dev))
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vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
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vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
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lane_mask);
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intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
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intel_dp_start_link_train(intel_dp);
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@ -1013,7 +1013,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe)
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}
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int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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struct intel_digital_port *dport);
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struct intel_digital_port *dport,
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unsigned int expected_mask);
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bool intel_get_load_detect_pipe(struct drm_connector *connector,
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struct drm_display_mode *mode,
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struct intel_load_detect_pipe *old,
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@ -1324,7 +1324,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
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intel_enable_hdmi(encoder);
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vlv_wait_port_ready(dev_priv, dport);
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vlv_wait_port_ready(dev_priv, dport, 0x0);
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}
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static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
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@ -1641,7 +1641,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
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intel_enable_hdmi(encoder);
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vlv_wait_port_ready(dev_priv, dport);
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vlv_wait_port_ready(dev_priv, dport, 0x0);
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}
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static void intel_hdmi_destroy(struct drm_connector *connector)
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