mirror of https://gitee.com/openkylin/linux.git
net/mlx5e: Add CQE compression user control
The user can now override the automatic driver decision using the rx_cqe_compress flag, which is the preference for CQE compression. The flag is initialized with the automatic driver decision. Signed-off-by: Shaker Daibes <shakerd@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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59ece1c969
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9bcc86064b
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@ -171,10 +171,12 @@ extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
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static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
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static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
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"rx_cqe_moder",
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"rx_cqe_moder",
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"rx_cqe_compress",
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};
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};
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enum mlx5e_priv_flag {
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enum mlx5e_priv_flag {
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MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
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MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
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MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
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};
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};
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#define MLX5E_SET_PFLAG(priv, pflag, enable) \
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#define MLX5E_SET_PFLAG(priv, pflag, enable) \
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@ -205,8 +207,7 @@ struct mlx5e_params {
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u16 num_channels;
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u16 num_channels;
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u8 num_tc;
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u8 num_tc;
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u8 rx_cq_period_mode;
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u8 rx_cq_period_mode;
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bool rx_cqe_compress_admin;
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bool rx_cqe_compress_def;
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bool rx_cqe_compress;
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struct mlx5e_cq_moder rx_cq_moderation;
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struct mlx5e_cq_moder rx_cq_moderation;
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struct mlx5e_cq_moder tx_cq_moderation;
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struct mlx5e_cq_moder tx_cq_moderation;
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u16 min_rx_wqes;
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u16 min_rx_wqes;
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@ -94,7 +94,7 @@ int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
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switch (config.rx_filter) {
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switch (config.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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case HWTSTAMP_FILTER_NONE:
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/* Reset CQE compression to Admin default */
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/* Reset CQE compression to Admin default */
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mlx5e_modify_rx_cqe_compression(priv, priv->params.rx_cqe_compress_admin);
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mlx5e_modify_rx_cqe_compression(priv, priv->params.rx_cqe_compress_def);
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break;
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break;
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_SOME:
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case HWTSTAMP_FILTER_SOME:
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@ -111,6 +111,7 @@ int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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/* Disable CQE compression */
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/* Disable CQE compression */
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netdev_warn(dev, "Disabling cqe compression");
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mlx5e_modify_rx_cqe_compression(priv, false);
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mlx5e_modify_rx_cqe_compression(priv, false);
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config.rx_filter = HWTSTAMP_FILTER_ALL;
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config.rx_filter = HWTSTAMP_FILTER_ALL;
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break;
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break;
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@ -1481,6 +1481,35 @@ static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
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return err;
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return err;
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}
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}
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static int set_pflag_rx_cqe_compress(struct net_device *netdev,
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bool enable)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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int err = 0;
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bool reset;
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if (!MLX5_CAP_GEN(mdev, cqe_compression))
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return -ENOTSUPP;
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if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
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netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
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return -EINVAL;
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}
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reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
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if (reset)
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mlx5e_close_locked(netdev);
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MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
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priv->params.rx_cqe_compress_def = enable;
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if (reset)
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err = mlx5e_open_locked(netdev);
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return err;
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}
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static int mlx5e_handle_pflag(struct net_device *netdev,
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static int mlx5e_handle_pflag(struct net_device *netdev,
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u32 wanted_flags,
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u32 wanted_flags,
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enum mlx5e_priv_flag flag,
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enum mlx5e_priv_flag flag,
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@ -1511,13 +1540,19 @@ static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
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int err;
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int err;
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mutex_lock(&priv->state_lock);
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mutex_lock(&priv->state_lock);
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err = mlx5e_handle_pflag(netdev, pflags,
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err = mlx5e_handle_pflag(netdev, pflags,
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MLX5E_PFLAG_RX_CQE_BASED_MODER,
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MLX5E_PFLAG_RX_CQE_BASED_MODER,
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set_pflag_rx_cqe_based_moder);
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set_pflag_rx_cqe_based_moder);
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if (err)
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goto out;
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err = mlx5e_handle_pflag(netdev, pflags,
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MLX5E_PFLAG_RX_CQE_COMPRESS,
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set_pflag_rx_cqe_compress);
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out:
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mutex_unlock(&priv->state_lock);
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mutex_unlock(&priv->state_lock);
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return err ? -EINVAL : 0;
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return err;
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}
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}
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static u32 mlx5e_get_priv_flags(struct net_device *netdev)
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static u32 mlx5e_get_priv_flags(struct net_device *netdev)
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@ -84,7 +84,8 @@ static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
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switch (priv->params.rq_wq_type) {
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switch (priv->params.rq_wq_type) {
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
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priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
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priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
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priv->params.mpwqe_log_stride_sz =
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MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
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MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
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MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
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MLX5_MPWRQ_LOG_STRIDE_SIZE;
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MLX5_MPWRQ_LOG_STRIDE_SIZE;
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priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
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priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
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@ -101,7 +102,7 @@ static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
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priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
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priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
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BIT(priv->params.log_rq_size),
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BIT(priv->params.log_rq_size),
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BIT(priv->params.mpwqe_log_stride_sz),
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BIT(priv->params.mpwqe_log_stride_sz),
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priv->params.rx_cqe_compress_admin);
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MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
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}
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}
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static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
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static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
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@ -1664,7 +1665,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
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}
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}
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MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
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MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
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if (priv->params.rx_cqe_compress) {
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if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
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MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
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MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
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MLX5_SET(cqc, cqc, cqe_comp_en, 1);
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MLX5_SET(cqc, cqc, cqe_comp_en, 1);
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}
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}
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@ -3447,17 +3448,16 @@ static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
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priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
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/* set CQE compression */
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/* set CQE compression */
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priv->params.rx_cqe_compress_admin = false;
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priv->params.rx_cqe_compress_def = false;
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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if (MLX5_CAP_GEN(mdev, cqe_compression) &&
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MLX5_CAP_GEN(mdev, vport_group_manager)) {
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MLX5_CAP_GEN(mdev, vport_group_manager)) {
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mlx5e_get_max_linkspeed(mdev, &link_speed);
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mlx5e_get_max_linkspeed(mdev, &link_speed);
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mlx5e_get_pci_bw(mdev, &pci_bw);
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mlx5e_get_pci_bw(mdev, &pci_bw);
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mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
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mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
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link_speed, pci_bw);
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link_speed, pci_bw);
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priv->params.rx_cqe_compress_admin =
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priv->params.rx_cqe_compress_def =
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cqe_compress_heuristic(link_speed, pci_bw);
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cqe_compress_heuristic(link_speed, pci_bw);
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}
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}
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priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
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mlx5e_set_rq_priv_params(priv);
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mlx5e_set_rq_priv_params(priv);
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if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
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if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
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@ -3490,6 +3490,7 @@ static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
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/* Initialize pflags */
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/* Initialize pflags */
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MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
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MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
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priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
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priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
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MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
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mutex_init(&priv->state_lock);
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mutex_init(&priv->state_lock);
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@ -164,14 +164,14 @@ void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
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mutex_lock(&priv->state_lock);
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mutex_lock(&priv->state_lock);
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if (priv->params.rx_cqe_compress == val)
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if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) == val)
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goto unlock;
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goto unlock;
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was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
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was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
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if (was_opened)
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if (was_opened)
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mlx5e_close_locked(priv->netdev);
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mlx5e_close_locked(priv->netdev);
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priv->params.rx_cqe_compress = val;
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MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, val);
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if (was_opened)
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if (was_opened)
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mlx5e_open_locked(priv->netdev);
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mlx5e_open_locked(priv->netdev);
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