mirror of https://gitee.com/openkylin/linux.git
net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
The mvneta is also used in some Marvell berlin family SoCs which may have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -260,7 +260,6 @@
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#define MVNETA_VLAN_TAG_LEN 4
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#define MVNETA_VLAN_TAG_LEN 4
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#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
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#define MVNETA_TX_CSUM_DEF_SIZE 1600
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#define MVNETA_TX_CSUM_DEF_SIZE 1600
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#define MVNETA_TX_CSUM_MAX_SIZE 9800
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#define MVNETA_TX_CSUM_MAX_SIZE 9800
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#define MVNETA_ACC_MODE_EXT1 1
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#define MVNETA_ACC_MODE_EXT1 1
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@ -300,7 +299,7 @@
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#define MVNETA_RX_PKT_SIZE(mtu) \
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#define MVNETA_RX_PKT_SIZE(mtu) \
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ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
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ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
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ETH_HLEN + ETH_FCS_LEN, \
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ETH_HLEN + ETH_FCS_LEN, \
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MVNETA_CPU_D_CACHE_LINE_SIZE)
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L1_CACHE_BYTES)
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#define IS_TSO_HEADER(txq, addr) \
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#define IS_TSO_HEADER(txq, addr) \
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((addr >= txq->tso_hdrs_phys) && \
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((addr >= txq->tso_hdrs_phys) && \
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@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
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if (rxq->descs == NULL)
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if (rxq->descs == NULL)
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return -ENOMEM;
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return -ENOMEM;
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BUG_ON(rxq->descs !=
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PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
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rxq->last_desc = rxq->size - 1;
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rxq->last_desc = rxq->size - 1;
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/* Set Rx descriptors queue starting address */
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/* Set Rx descriptors queue starting address */
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@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp,
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if (txq->descs == NULL)
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if (txq->descs == NULL)
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return -ENOMEM;
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return -ENOMEM;
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/* Make sure descriptor address is cache line size aligned */
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BUG_ON(txq->descs !=
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PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
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txq->last_desc = txq->size - 1;
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txq->last_desc = txq->size - 1;
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/* Set maximum bandwidth for enabled TXQs */
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/* Set maximum bandwidth for enabled TXQs */
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