mirror of https://gitee.com/openkylin/linux.git
- fixes for boot breakage because of misaligned FDTs
- fix for overwritten exception handlers - enable MIPS optimized crypto for all MIPS CPUs to improve wireguard performance -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmBHkMwaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHBxRg/+JKKRLn2GyQkqLVkBKCRk mKQkqyRAP3HdwBN1EsC2K8PWhoffc577byyO+R+nXDR9BUSrK1geTrwdtOAH/ZMa sX/YqvJdyzS5HqAIkSy1KyzoYOWFB/Xe0VsLn85Oz5QMR+OWzcdG06LcKq+v4fro za47T6hufjN179EhYOP+xldMwkhfK/fMw4HKFoOY9swaGhCVHx9PSoCb8dyd9vhQ X3il5l2BlihcJKAitLErUrxciu6eLiUEB3ODbj6HQM3yjJeRiwK20PJfsfy1QIWn 44dNz5cI1XRlWk4HdNGfZ5/8VV0gMVv3UKK1SPyiBk1o+CRlh/qtxtvjHejm6c2+ 56iQsYk/XYjFSMZf3WgLzZJoxWGll+ParIFxEJ4SfxFMFDe/KtcvdMhqwy2zJJKq cZc17sT3YHIHdelDYpYt0T7TZxFxnj18BWwOWVsvNEMKCGxOUetH2MrOlsi5aIHh mSYtsQ6V6FXZKlRgHAVnPL6gxPtlhIjbru7Zv9eW8wRUrB/pQWy6OGoWTR1B0sKr TdbmfEbnIKpSEE6WSugGpnflNsIWJYrZXePTBRCibipQZVCmcyhiphSQb0UiNKOO uzWnLYGToL+gpRjC/GNEcjycQvT4rUzHUCpnH3s99VfabkQzcgYT+9m7ORsbdKm5 r9mTuB7X7WYiMcOXTtPBX3A= =xWSR -----END PGP SIGNATURE----- Merge tag 'mips-fixes_5.12_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Thomas Bogendoerfer: - fixes for boot breakage because of misaligned FDTs - fix for overwritten exception handlers - enable MIPS optimized crypto for all MIPS CPUs to improve wireguard performance * tag 'mips-fixes_5.12_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: kernel: Reserve exception base early to prevent corruption MIPS: vmlinux.lds.S: align raw appended dtb to 8 bytes crypto: mips/poly1305 - enable for all MIPS processors MIPS: boot/compressed: Copy DTB to aligned address
This commit is contained in:
Linus Torvalds
commit
9c39198a65
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@ -14,6 +14,7 @@
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#include <asm/addrspace.h>
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#include <asm/unaligned.h>
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#include <asm-generic/vmlinux.lds.h>
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/*
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* These two variables specify the free mem region
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@ -120,6 +121,13 @@ void decompress_kernel(unsigned long boot_heap_start)
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/* last four bytes is always image size in little endian */
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image_size = get_unaligned_le32((void *)&__image_end - 4);
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/* The device tree's address must be properly aligned */
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image_size = ALIGN(image_size, STRUCT_ALIGNMENT);
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puts("Copy device tree to address ");
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puthex(VMLINUX_LOAD_ADDRESS_ULL + image_size);
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puts("\n");
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/* copy dtb to where the booted kernel will expect it */
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memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,
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__appended_dtb, dtb_size);
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@ -12,8 +12,8 @@ AFLAGS_chacha-core.o += -O2 # needed to fill branch delay slots
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obj-$(CONFIG_CRYPTO_POLY1305_MIPS) += poly1305-mips.o
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poly1305-mips-y := poly1305-core.o poly1305-glue.o
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perlasm-flavour-$(CONFIG_CPU_MIPS32) := o32
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perlasm-flavour-$(CONFIG_CPU_MIPS64) := 64
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perlasm-flavour-$(CONFIG_32BIT) := o32
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perlasm-flavour-$(CONFIG_64BIT) := 64
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quiet_cmd_perlasm = PERLASM $@
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cmd_perlasm = $(PERL) $(<) $(perlasm-flavour-y) $(@)
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@ -24,8 +24,11 @@ extern void (*board_ebase_setup)(void);
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extern void (*board_cache_error_setup)(void);
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extern int register_nmi_notifier(struct notifier_block *nb);
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extern void reserve_exception_space(phys_addr_t addr, unsigned long size);
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extern char except_vec_nmi[];
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#define VECTORSPACING 0x100 /* for EI/VI mode */
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#define nmi_notifier(fn, pri) \
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({ \
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static struct notifier_block fn##_nb = { \
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@ -26,6 +26,7 @@
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#include <asm/elf.h>
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#include <asm/pgtable-bits.h>
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#include <asm/spram.h>
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#include <asm/traps.h>
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#include <linux/uaccess.h>
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#include "fpu-probe.h"
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@ -1628,6 +1629,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_BMIPS3300;
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__cpu_name[cpu] = "Broadcom BMIPS3300";
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set_elf_platform(cpu, "bmips3300");
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reserve_exception_space(0x400, VECTORSPACING * 64);
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break;
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case PRID_IMP_BMIPS43XX: {
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int rev = c->processor_id & PRID_REV_MASK;
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@ -1638,6 +1640,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "Broadcom BMIPS4380";
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set_elf_platform(cpu, "bmips4380");
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c->options |= MIPS_CPU_RIXI;
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reserve_exception_space(0x400, VECTORSPACING * 64);
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} else {
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c->cputype = CPU_BMIPS4350;
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__cpu_name[cpu] = "Broadcom BMIPS4350";
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@ -1654,6 +1657,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "Broadcom BMIPS5000";
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set_elf_platform(cpu, "bmips5000");
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c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
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reserve_exception_space(0x1000, VECTORSPACING * 64);
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break;
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}
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}
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@ -2133,6 +2137,8 @@ void cpu_probe(void)
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if (cpu == 0)
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__ua_limit = ~((1ull << cpu_vmbits) - 1);
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#endif
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reserve_exception_space(0, 0x1000);
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}
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void cpu_report(void)
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@ -21,6 +21,7 @@
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/elf.h>
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#include <asm/traps.h>
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#include "fpu-probe.h"
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@ -158,6 +159,8 @@ void cpu_probe(void)
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cpu_set_fpu_opts(c);
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else
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cpu_set_nofpu_opts(c);
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reserve_exception_space(0, 0x400);
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}
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void cpu_report(void)
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@ -2009,13 +2009,16 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
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nmi_exit();
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}
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#define VECTORSPACING 0x100 /* for EI/VI mode */
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unsigned long ebase;
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EXPORT_SYMBOL_GPL(ebase);
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unsigned long exception_handlers[32];
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unsigned long vi_handlers[64];
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void reserve_exception_space(phys_addr_t addr, unsigned long size)
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{
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memblock_reserve(addr, size);
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}
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void __init *set_except_vector(int n, void *addr)
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{
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unsigned long handler = (unsigned long) addr;
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@ -2367,10 +2370,7 @@ void __init trap_init(void)
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if (!cpu_has_mips_r2_r6) {
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ebase = CAC_BASE;
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ebase_pa = virt_to_phys((void *)ebase);
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vec_size = 0x400;
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memblock_reserve(ebase_pa, vec_size);
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} else {
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if (cpu_has_veic || cpu_has_vint)
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vec_size = 0x200 + VECTORSPACING*64;
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@ -145,6 +145,7 @@ SECTIONS
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}
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#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
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STRUCT_ALIGN();
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.appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
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*(.appended_dtb)
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KEEP(*(.appended_dtb))
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@ -172,6 +173,11 @@ SECTIONS
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#endif
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#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
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.fill : {
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FILL(0);
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BYTE(0);
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. = ALIGN(8);
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}
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__appended_dtb = .;
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/* leave space for appended DTB */
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. += 0x100000;
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@ -767,7 +767,7 @@ config CRYPTO_POLY1305_X86_64
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config CRYPTO_POLY1305_MIPS
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tristate "Poly1305 authenticator algorithm (MIPS optimized)"
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depends on CPU_MIPS32 || (CPU_MIPS64 && 64BIT)
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depends on MIPS
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select CRYPTO_ARCH_HAVE_LIB_POLY1305
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config CRYPTO_MD4
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@ -94,7 +94,7 @@ config WIREGUARD
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select CRYPTO_BLAKE2S_ARM if ARM
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select CRYPTO_CURVE25519_NEON if ARM && KERNEL_MODE_NEON
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select CRYPTO_CHACHA_MIPS if CPU_MIPS32_R2
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select CRYPTO_POLY1305_MIPS if CPU_MIPS32 || (CPU_MIPS64 && 64BIT)
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select CRYPTO_POLY1305_MIPS if MIPS
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help
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WireGuard is a secure, fast, and easy to use replacement for IPSec
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that uses modern cryptography and clever networking tricks. It's
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