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powerpc/44x/fsp2: Interrupt handling setup 

* clear out any possible plb6 errors
* board interrupt handling setup within l2 reg set
* fsp2 parity error setup

All those points are needed for correct interrupt
handling on board level including error handling report.

Reviewed-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Ivan Mikhaylov 2017-12-01 18:58:25 +03:00 committed by Michael Ellerman
parent 494d82ceae
commit 9c4c374676
1 changed files with 37 additions and 0 deletions
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37
arch/powerpc/platforms/44x/fsp2.c
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@ -27,6 +27,8 @@
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/ppc4xx.h>
#include <asm/dcr.h>
#include "fsp2.h"
static __initdata struct of_device_id fsp2_of_bus[] = {
{ .compatible = "ibm,plb4", },
@ -44,10 +46,45 @@ machine_device_initcall(fsp2, fsp2_device_probe);
static int __init fsp2_probe(void)
{
u32 val;
unsigned long root = of_get_flat_dt_root();
if (!of_flat_dt_is_compatible(root, "ibm,fsp2"))
return 0;
/* Clear BC_ERR and mask snoopable request plb errors. */
val = mfdcr(DCRN_PLB6_CR0);
val |= 0x20000000;
mtdcr(DCRN_PLB6_BASE, val);
mtdcr(DCRN_PLB6_HD, 0xffff0000);
mtdcr(DCRN_PLB6_SHD, 0xffff0000);
/* L2 machine checks */
mtl2(L2PLBMCKEN0, 0xffffffff);
mtl2(L2PLBMCKEN1, 0x0000ffff);
mtl2(L2ARRMCKEN0, 0xffffffff);
mtl2(L2ARRMCKEN1, 0xffffffff);
mtl2(L2ARRMCKEN2, 0xfffff000);
mtl2(L2CPUMCKEN, 0xffffffff);
mtl2(L2RACMCKEN0, 0xffffffff);
mtl2(L2WACMCKEN0, 0xffffffff);
mtl2(L2WACMCKEN1, 0xffffffff);
mtl2(L2WACMCKEN2, 0xffffffff);
mtl2(L2WDFMCKEN, 0xffffffff);
/* L2 interrupts */
mtl2(L2PLBINTEN1, 0xffff0000);
/*
* At a global level, enable all L2 machine checks and interrupts
* reported by the L2 subsystems, except for the external machine check
* input (UIC0.1).
*/
mtl2(L2MCKEN, 0x000007ff);
mtl2(L2INTEN, 0x000004ff);
/* Enable FSP-2 configuration logic parity errors */
mtdcr(DCRN_CONF_EIR_RS, 0x80000000);
return 1;
}