mirror of https://gitee.com/openkylin/linux.git
ARM: OMAP2+: Add support for initializing dm814x clocks
Let's add a minimal clocks for dm814x to get it booted. This is mostly a placeholder and relies on the PLLs being on from the bootloader. Note that the divider clocks work the same way as on dm816x and am335x. Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -558,7 +558,7 @@ void __init ti814x_init_early(void)
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ti81xx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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omap_clk_soc_init = dm814x_dt_clk_init;
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}
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void __init ti816x_init_early(void)
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@ -575,7 +575,7 @@ void __init ti816x_init_early(void)
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ti81xx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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omap_clk_soc_init = dm816x_dt_clk_init;
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}
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#endif
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@ -2,7 +2,7 @@ obj-y += clk.o autoidle.o clockdomain.o
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clk-common = dpll.o composite.o divider.o gate.o \
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fixed-factor.o mux.o apll.o
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obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
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clk-3xxx.o
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@ -0,0 +1,31 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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static struct ti_dt_clk dm814_clks[] = {
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DT_CLK(NULL, "devosc_ck", "devosc_ck"),
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DT_CLK(NULL, "mpu_ck", "mpu_ck"),
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DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
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DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
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DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
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DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
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DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
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DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
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DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
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{ .node_name = NULL },
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};
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int __init dm814x_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm814_clks);
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omap2_clk_disable_autoidle_all();
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omap2_clk_enable_init_clocks(NULL, 0);
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return 0;
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}
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@ -42,7 +42,7 @@ static const char *enable_init_clks[] = {
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"ddr_pll_clk3",
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};
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int __init ti81xx_dt_clk_init(void)
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int __init dm816x_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm816x_clks);
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omap2_clk_disable_autoidle_all();
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@ -329,7 +329,8 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
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int omap3430_dt_clk_init(void);
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int omap3630_dt_clk_init(void);
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int am35xx_dt_clk_init(void);
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int ti81xx_dt_clk_init(void);
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int dm814x_dt_clk_init(void);
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int dm816x_dt_clk_init(void);
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int omap4xxx_dt_clk_init(void);
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int omap5xxx_dt_clk_init(void);
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int dra7xx_dt_clk_init(void);
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