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drm/nouveau/gr/gf100-: virtualise r4060a8 + apply fixes from traces 

Also fixes some GPUs where we write too many registers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent e51f75d501
commit 9d8a80df73
7 changed files with 15 additions and 5 deletions
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11
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View File

@ -1083,7 +1083,9 @@ void
gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u8 tpcnr[GPC_MAX], data[TPC_MAX];
const u8 gpcmax = nvkm_rd32(device, 0x022430);
const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax;
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
@ -1098,7 +1100,7 @@ gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
data[tpc] = gpc;
}
for (i = 0; i < 4; i++)
for (i = 0; i < DIV_ROUND_UP(tpcmax, 4); i++)
nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
}
@ -1236,6 +1238,9 @@ gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
nvkm_wr32(device, 0x406028 + (i * 4), data);
nvkm_wr32(device, 0x405870 + (i * 4), data);
}
if (func->r4060a8)
func->r4060a8(gr);
}
void
@ -1267,7 +1272,6 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
gf100_grctx_generate_r4060a8(gr);
gf100_grctx_generate_r418bb8(gr);
gf100_grctx_generate_r406800(gr);
@ -1419,4 +1423,5 @@ gf100_grctx = {
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View File

@ -53,6 +53,7 @@ struct gf100_grctx_func {
/* floorsweeping */
void (*sm_id)(struct gf100_gr *, int gpc, int tpc, int sm);
void (*tpc_nr)(struct gf100_gr *, int gpc);
void (*r4060a8)(struct gf100_gr *);
};
extern const struct gf100_grctx_func gf100_grctx;
@ -63,11 +64,11 @@ void gf100_grctx_generate_pagepool(struct gf100_grctx *);
void gf100_grctx_generate_attrib(struct gf100_grctx *);
void gf100_grctx_generate_unkn(struct gf100_gr *);
void gf100_grctx_generate_floorsweep(struct gf100_gr *);
void gf100_grctx_generate_r4060a8(struct gf100_gr *);
void gf100_grctx_generate_r418bb8(struct gf100_gr *);
void gf100_grctx_generate_r406800(struct gf100_gr *);
void gf100_grctx_generate_sm_id(struct gf100_gr *, int, int, int);
void gf100_grctx_generate_tpc_nr(struct gf100_gr *, int);
void gf100_grctx_generate_r4060a8(struct gf100_gr *);
extern const struct gf100_grctx_func gf108_grctx;
void gf108_grctx_generate_attrib(struct gf100_grctx *);

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
View File

@ -98,4 +98,5 @@ gf104_grctx = {
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
View File

@ -796,4 +796,5 @@ gf108_grctx = {
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
View File

@ -349,4 +349,5 @@ gf110_grctx = {
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
View File

@ -241,7 +241,6 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
gf100_grctx_generate_r4060a8(gr);
gk104_grctx_generate_r418bb8(gr);
gf100_grctx_generate_r406800(gr);
@ -276,4 +275,5 @@ gf117_grctx = {
.alpha_nr = 0x324,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
View File

@ -519,4 +519,5 @@ gf119_grctx = {
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
};