mirror of https://gitee.com/openkylin/linux.git
staging: comedi: drivers: re-do PLX PCI 9080 INTCSR register values
Replace the existing macros in "plx9080.h" that define values for the INTCSR register. Use the prefix `PLX_INTCSR_` for the macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define the values. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott
Greg Kroah-Hartman
parent
ed5df5db92
commit
9dc53852b1
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@ -1336,8 +1336,9 @@ static void init_plx9080(struct comedi_device *dev)
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/* enable interrupts on plx 9080 */
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devpriv->plx_intcsr_bits |=
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ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
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ICS_DMA0_E | ICS_DMA1_E;
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PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
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PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
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PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
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writel(devpriv->plx_intcsr_bits,
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devpriv->plx9080_iobase + PLX_REG_INTCSR);
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}
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@ -2836,7 +2837,7 @@ static void handle_ai_interrupt(struct comedi_device *dev,
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/* spin lock makes sure no one else changes plx dma control reg */
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spin_lock_irqsave(&dev->spinlock, flags);
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dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
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if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
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if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
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writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
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devpriv->plx9080_iobase + PLX_REG_DMACSR1);
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@ -3014,7 +3015,7 @@ static void handle_ao_interrupt(struct comedi_device *dev,
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/* spin lock makes sure no one else changes plx dma control reg */
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spin_lock_irqsave(&dev->spinlock, flags);
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dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
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if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
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if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
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if ((dma0_status & PLX_DMA_EN_BIT) &&
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!(dma0_status & PLX_DMA_DONE_BIT)) {
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writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
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@ -3068,7 +3069,8 @@ static irqreturn_t handle_interrupt(int irq, void *d)
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handle_ao_interrupt(dev, status, plx_status);
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/* clear possible plx9080 interrupt sources */
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if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
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if (plx_status & PLX_INTCSR_LDBIA) {
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/* clear local doorbell interrupt */
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plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
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writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
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}
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@ -199,7 +199,8 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
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return IRQ_NONE;
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plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
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if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
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if ((plx_status &
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(PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
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return IRQ_NONE;
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hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
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@ -211,7 +212,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
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/* spin lock makes sure no one else changes plx dma control reg */
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spin_lock_irqsave(&dev->spinlock, flags);
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dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
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if (plx_status & ICS_DMA0_A) {
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if (plx_status & PLX_INTCSR_DMA0IA) {
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/* dma chan 0 interrupt */
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writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
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devpriv->plx9080_mmio + PLX_REG_DMACSR0);
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@ -224,7 +225,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
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/* spin lock makes sure no one else changes plx dma control reg */
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spin_lock_irqsave(&dev->spinlock, flags);
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dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
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if (plx_status & ICS_DMA1_A) {
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if (plx_status & PLX_INTCSR_DMA1IA) {
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/* XXX */ /* dma chan 1 interrupt */
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writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
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devpriv->plx9080_mmio + PLX_REG_DMACSR1);
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@ -232,7 +233,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
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spin_unlock_irqrestore(&dev->spinlock, flags);
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/* clear possible plx9080 interrupt sources */
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if (plx_status & ICS_LDIA) {
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if (plx_status & PLX_INTCSR_LDBIA) {
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/* clear local doorbell interrupt */
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plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
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writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
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@ -533,8 +534,9 @@ static int gsc_hpdi_init(struct comedi_device *dev)
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/* enable interrupts */
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plx_intcsr_bits =
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ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
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ICS_DMA0_E;
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PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
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PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
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PLX_INTCSR_DMA0IEN;
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writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
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return 0;
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@ -321,32 +321,71 @@ struct plx_dma_desc {
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/* Interrupt Control/Status Register */
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#define PLX_REG_INTCSR 0x0068
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#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */
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#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */
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#define ICS_SERR 0x00000004 /* Generate PCI SERR# */
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#define ICS_MBIE 0x00000008 /* mailbox interrupt enable */
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#define ICS_PIE 0x00000100 /* PCI Interrupt Enable */
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#define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */
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#define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */
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#define ICS_PLIE 0x00000800 /* PCI Local Int Enable */
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#define ICS_RAE 0x00001000 /* Retry Abort Enable */
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#define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */
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#define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */
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#define ICS_LIA 0x00008000 /* Local Interrupt Active */
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#define ICS_LIE 0x00010000 /* Local Interrupt Enable */
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#define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */
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#define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */
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#define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */
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#define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */
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#define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */
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#define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */
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#define ICS_BIA 0x00800000 /* BIST Interrupt Active */
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#define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */
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#define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */
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#define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */
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#define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */
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/* mailbox x is active */
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#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3))
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/* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
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#define PLX_INTCSR_LSEABORTEN BIT(0)
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/* Enable Local Bus LSERR# when PCI parity error occurs */
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#define PLX_INTCSR_LSEPARITYEN BIT(1)
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/* Generate PCI Bus SERR# when set to 1 */
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#define PLX_INTCSR_GENSERR BIT(2)
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/* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
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#define PLX_INTCSR_MBIEN BIT(3)
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/* PCI Interrupt Enable */
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#define PLX_INTCSR_PIEN BIT(8)
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/* PCI Doorbell Interrupt Enable */
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#define PLX_INTCSR_PDBIEN BIT(9)
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/* PCI Abort Interrupt Enable */
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#define PLX_INTCSR_PABORTIEN BIT(10)
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/* PCI Local Interrupt Enable */
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#define PLX_INTCSR_PLIEN BIT(11)
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/* Retry Abort Enable (for diagnostic purposes only) */
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#define PLX_INTCSR_RAEN BIT(12)
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/* PCI Doorbell Interrupt Active (read-only) */
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#define PLX_INTCSR_PDBIA BIT(13)
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/* PCI Abort Interrupt Active (read-only) */
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#define PLX_INTCSR_PABORTIA BIT(14)
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/* Local Interrupt (LINTi#) Active (read-only) */
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#define PLX_INTCSR_PLIA BIT(15)
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/* Local Interrupt Output (LINTo#) Enable */
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#define PLX_INTCSR_LIOEN BIT(16)
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/* Local Doorbell Interrupt Enable */
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#define PLX_INTCSR_LDBIEN BIT(17)
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/* DMA Channel 0 Interrupt Enable */
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#define PLX_INTCSR_DMA0IEN BIT(18)
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/* DMA Channel 1 Interrupt Enable */
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#define PLX_INTCSR_DMA1IEN BIT(19)
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/* DMA Channel N Interrupt Enable (N <= 1) */
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#define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN)
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/* Local Doorbell Interrupt Active (read-only) */
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#define PLX_INTCSR_LDBIA BIT(20)
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/* DMA Channel 0 Interrupt Active (read-only) */
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#define PLX_INTCSR_DMA0IA BIT(21)
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/* DMA Channel 1 Interrupt Active (read-only) */
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#define PLX_INTCSR_DMA1IA BIT(22)
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/* DMA Channel N Interrupt Active (N <= 1) (read-only) */
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#define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA)
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/* BIST Interrupt Active (read-only) */
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#define PLX_INTCSR_BISTIA BIT(23)
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/* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
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#define PLX_INTCSR_ABNOTDM BIT(24)
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/* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
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#define PLX_INTCSR_ABNOTDMA0 BIT(25)
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/* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
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#define PLX_INTCSR_ABNOTDMA1 BIT(26)
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/* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
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#define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \
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: PLX_INTCSR_ABNOTDMA0)
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/* Target Abort Not Generated After 256 Master Retries (read-only) */
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#define PLX_INTCSR_ABNOTRETRY BIT(27)
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/* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
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#define PLX_INTCSR_MB0IA BIT(28)
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/* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
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#define PLX_INTCSR_MB1IA BIT(29)
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/* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
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#define PLX_INTCSR_MB2IA BIT(30)
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/* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
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#define PLX_INTCSR_MB3IA BIT(31)
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/* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
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#define PLX_INTCSR_MBIA(n) BIT(28 + (n))
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/*
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* Serial EEPROM Control, PCI Command Codes, User I/O Control,
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@ -1316,7 +1316,8 @@ static int rtd_auto_attach(struct comedi_device *dev,
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devpriv->fifosz = ret;
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if (dev->irq)
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writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_REG_INTCSR);
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writel(PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN,
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devpriv->lcfg + PLX_REG_INTCSR);
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return 0;
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}
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