mirror of https://gitee.com/openkylin/linux.git
can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS
In order to receive RTR frames in the non HW FIFO mode the RSS and EACEN bits of the reg_ctrl2 have to be activated. As this has no side effect in the FIFO mode, we do this unconditionally on cores with the reg_ctrl2. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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@ -187,7 +187,8 @@
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*/
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#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
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#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
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#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disble Memory error detection */
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/* Structure of the message buffer */
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struct flexcan_mb {
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@ -276,11 +277,12 @@ static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
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static const struct flexcan_devtype_data fsl_imx28_devtype_data;
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static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
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.quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
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.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS,
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};
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static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
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.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
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.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
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FLEXCAN_QUIRK_DISABLE_MECR,
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};
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static const struct can_bittiming_const flexcan_bittiming_const = {
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@ -825,6 +827,12 @@ static int flexcan_chip_start(struct net_device *dev)
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netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
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flexcan_write(reg_ctrl, ®s->ctrl);
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if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
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reg_ctrl2 = flexcan_read(®s->ctrl2);
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reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
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flexcan_write(reg_ctrl2, ®s->ctrl2);
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}
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/* clear and invalidate all mailboxes first */
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for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
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flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
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