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ARM: imx: new Kconfig symbol and feature test macro for DMA on mx1 and mx2
This should be used instead of hard coding the corresponding platforms. The feature test macro is needed to support different SOCs in a single kernel image. While at it rename dma-mx1-mx2 to dma-v1 as mx25 doesn't use it and so the mx2 part is wrong and move the header to arch/arm/mach-imx. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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@ -1,7 +1,11 @@
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config IMX_HAVE_DMA_V1
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bool
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if ARCH_MX1
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config SOC_IMX1
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select CPU_ARM920T
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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bool
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@ -27,12 +31,14 @@ if ARCH_MX2
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config SOC_IMX21
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select CPU_ARM926T
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select ARCH_MXC_AUDMUX_V1
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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bool
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config SOC_IMX27
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select CPU_ARM926T
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select ARCH_MXC_AUDMUX_V1
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select IMX_HAVE_DMA_V1
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select IMX_HAVE_IOMUX_V1
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bool
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@ -6,6 +6,8 @@
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obj-y := devices.o
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obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
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obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
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obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/plat-mxc/dma-mx1-mx2.c
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* linux/arch/arm/plat-mxc/dma-v1.c
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*
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* i.MX DMA registration and IRQ dispatching
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*
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@ -34,7 +34,7 @@
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/dma-mx1-mx2.h>
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#include <mach/dma-v1.h>
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#define DMA_DCR 0x00 /* Control Register */
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#define DMA_DISR 0x04 /* Interrupt status Register */
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@ -0,0 +1,10 @@
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#ifndef __MACH_DMA_MX1_MX2_H__
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#define __MACH_DMA_MX1_MX2_H__
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/*
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* Don't use this header in new code, it will go away when all users are
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* converted to mach/dma-v1.h
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*/
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#include <mach/dma-v1.h>
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#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
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* linux/arch/arm/mach-imx/include/mach/dma-v1.h
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*
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* i.MX DMA registration and IRQ dispatching
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*
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@ -22,8 +22,10 @@
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_DMA_H
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#define __ASM_ARCH_MXC_DMA_H
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#ifndef __MACH_DMA_V1_H__
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#define __MACH_DMA_V1_H__
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#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
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#define IMX_DMA_CHANNELS 16
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@ -102,4 +104,4 @@ enum imx_dma_prio {
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int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
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#endif /* _ASM_ARCH_MXC_DMA_H */
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#endif /* __MACH_DMA_V1_H__ */
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@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
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# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
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obj-$(CONFIG_MXC_TZIC) += tzic.o
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obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
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obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
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obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
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obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
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obj-$(CONFIG_MXC_PWM) += pwm.o
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