mirror of https://gitee.com/openkylin/linux.git
drm/nv50-: prevent some races between modesetting and page flipping
nexuiz-glx + gnome-shell is able to trigger this a lot of the time. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
42bed34c36
commit
9f9bdaaf07
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@ -55,9 +55,9 @@
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/* offsets in shared sync bo of various structures */
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#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
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#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
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#define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
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#define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
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#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
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#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
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#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
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#define EVO_CORE_HANDLE (0xd1500000)
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#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
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@ -341,10 +341,8 @@ struct nv50_curs {
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struct nv50_sync {
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struct nv50_dmac base;
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struct {
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u32 offset;
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u16 value;
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} sem;
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u32 addr;
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u32 data;
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};
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struct nv50_ovly {
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@ -471,13 +469,33 @@ nv50_display_crtc_sema(struct drm_device *dev, int crtc)
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return nv50_disp(dev)->sync;
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}
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struct nv50_display_flip {
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struct nv50_disp *disp;
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struct nv50_sync *chan;
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};
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static bool
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nv50_display_flip_wait(void *data)
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{
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struct nv50_display_flip *flip = data;
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if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
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flip->chan->data);
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return true;
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usleep_range(1, 2);
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return false;
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}
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void
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nv50_display_flip_stop(struct drm_crtc *crtc)
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{
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struct nv50_sync *sync = nv50_sync(crtc);
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struct nouveau_device *device = nouveau_dev(crtc->dev);
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struct nv50_display_flip flip = {
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.disp = nv50_disp(crtc->dev),
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.chan = nv50_sync(crtc),
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};
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u32 *push;
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push = evo_wait(sync, 8);
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push = evo_wait(flip.chan, 8);
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if (push) {
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x00000000);
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@ -487,8 +505,10 @@ nv50_display_flip_stop(struct drm_crtc *crtc)
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0080, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, sync);
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evo_kick(push, flip.chan);
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}
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nv_wait_cb(device, nv50_display_flip_wait, &flip);
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}
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int
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@ -496,11 +516,10 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct nouveau_channel *chan, u32 swap_interval)
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{
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struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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struct nv50_disp *disp = nv50_disp(crtc->dev);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nv50_sync *sync = nv50_sync(crtc);
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int head = nv_crtc->index, ret;
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u32 *push;
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int ret;
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swap_interval <<= 4;
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if (swap_interval == 0)
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@ -510,66 +529,64 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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if (unlikely(push == NULL))
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return -EBUSY;
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/* synchronise with the rendering channel, if necessary */
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if (likely(chan)) {
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if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
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ret = RING_SPACE(chan, 8);
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if (ret)
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return ret;
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if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
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ret = RING_SPACE(chan, 8);
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if (ret)
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return ret;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
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OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
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OUT_RING (chan, sync->sem.offset);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
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OUT_RING (chan, 0xf00d0000 | sync->sem.value);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
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OUT_RING (chan, sync->sem.offset ^ 0x10);
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OUT_RING (chan, 0x74b1e000);
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} else
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if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
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u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
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offset += sync->sem.offset;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
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OUT_RING (chan, NvEvoSema0 + head);
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OUT_RING (chan, sync->addr ^ 0x10);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
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OUT_RING (chan, sync->data + 1);
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
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OUT_RING (chan, sync->addr);
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OUT_RING (chan, sync->data);
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} else
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if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
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u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
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ret = RING_SPACE(chan, 12);
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if (ret)
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return ret;
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ret = RING_SPACE(chan, 12);
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if (ret)
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return ret;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, chan->vram);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr ^ 0x10));
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OUT_RING (chan, lower_32_bits(addr ^ 0x10));
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OUT_RING (chan, sync->data + 1);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, sync->data);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
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} else
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if (chan) {
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u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
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ret = RING_SPACE(chan, 10);
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if (ret)
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return ret;
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, chan->vram);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset));
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OUT_RING (chan, 0xf00d0000 | sync->sem.value);
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OUT_RING (chan, 0x00000002);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset ^ 0x10));
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OUT_RING (chan, 0x74b1e000);
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OUT_RING (chan, 0x00000001);
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} else {
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u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
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offset += sync->sem.offset;
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ret = RING_SPACE(chan, 10);
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if (ret)
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return ret;
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset));
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OUT_RING (chan, 0xf00d0000 | sync->sem.value);
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OUT_RING (chan, 0x00001002);
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset ^ 0x10));
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OUT_RING (chan, 0x74b1e000);
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OUT_RING (chan, 0x00001001);
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}
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr ^ 0x10));
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OUT_RING (chan, lower_32_bits(addr ^ 0x10));
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OUT_RING (chan, sync->data + 1);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
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NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(addr));
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OUT_RING (chan, lower_32_bits(addr));
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OUT_RING (chan, sync->data);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
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NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
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}
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if (chan) {
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sync->addr ^= 0x10;
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sync->data++;
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FIRE_RING (chan);
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} else {
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nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
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0xf00d0000 | sync->sem.value);
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evo_sync(crtc->dev);
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}
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@ -583,9 +600,9 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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evo_data(push, 0x40000000);
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}
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evo_mthd(push, 0x0088, 4);
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evo_data(push, sync->sem.offset);
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evo_data(push, 0xf00d0000 | sync->sem.value);
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evo_data(push, 0x74b1e000);
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evo_data(push, sync->addr);
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evo_data(push, sync->data++);
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evo_data(push, sync->data);
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evo_data(push, NvEvoSync);
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evo_mthd(push, 0x00a0, 2);
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evo_data(push, 0x00000000);
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@ -613,9 +630,6 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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evo_mthd(push, 0x0080, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, sync);
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sync->sem.offset ^= 0x10;
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sync->sem.value++;
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return 0;
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}
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@ -1387,7 +1401,8 @@ nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
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if (ret)
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goto out;
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head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
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head->sync.addr = EVO_FLIP_SEM0(index);
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head->sync.data = 0x00000000;
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/* allocate overlay resources */
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ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
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@ -2120,15 +2135,23 @@ nv50_display_fini(struct drm_device *dev)
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int
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nv50_display_init(struct drm_device *dev)
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{
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u32 *push = evo_wait(nv50_mast(dev), 32);
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if (push) {
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evo_mthd(push, 0x0088, 1);
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evo_data(push, NvEvoSync);
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evo_kick(push, nv50_mast(dev));
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return 0;
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struct nv50_disp *disp = nv50_disp(dev);
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struct drm_crtc *crtc;
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u32 *push;
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push = evo_wait(nv50_mast(dev), 32);
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if (!push)
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return -EBUSY;
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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struct nv50_sync *sync = nv50_sync(crtc);
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nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
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}
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return -EBUSY;
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evo_mthd(push, 0x0088, 1);
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evo_data(push, NvEvoSync);
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evo_kick(push, nv50_mast(dev));
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return 0;
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}
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void
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