mirror of https://gitee.com/openkylin/linux.git
MIPS: KVM: Arrayify struct kvm_mips_tlb::tlb_lo*
The values of the EntryLo0 and EntryLo1 registers for a TLB entry are stored in separate members of struct kvm_mips_tlb called tlb_lo0 and tlb_lo1 respectively. To allow future code which needs to manipulate arbitrary EntryLo data in the TLB entry to be simpler and less conditional, replace these members with an array of two elements. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -310,13 +310,13 @@ enum emulation_result {
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#define VPN2_MASK 0xffffe000
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#define VPN2_MASK 0xffffe000
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#define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
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#define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
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#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
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#define TLB_IS_GLOBAL(x) (((x).tlb_lo[0] & MIPS3_PG_G) && \
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((x).tlb_lo1 & MIPS3_PG_G))
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((x).tlb_lo[1] & MIPS3_PG_G))
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#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
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#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
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#define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
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#define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
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#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
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#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
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? ((x).tlb_lo1 & MIPS3_PG_V) \
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? ((x).tlb_lo[1] & MIPS3_PG_V) \
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: ((x).tlb_lo0 & MIPS3_PG_V))
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: ((x).tlb_lo[0] & MIPS3_PG_V))
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#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
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#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
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((y) & VPN2_MASK & ~(x).tlb_mask))
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((y) & VPN2_MASK & ~(x).tlb_mask))
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#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
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#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
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@ -325,8 +325,7 @@ enum emulation_result {
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struct kvm_mips_tlb {
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struct kvm_mips_tlb {
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long tlb_mask;
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long tlb_mask;
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long tlb_hi;
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long tlb_hi;
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long tlb_lo0;
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long tlb_lo[2];
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long tlb_lo1;
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};
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};
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#define KVM_MIPS_FPU_FPU 0x1
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#define KVM_MIPS_FPU_FPU 0x1
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@ -833,8 +833,8 @@ enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
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tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
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tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
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tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
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tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
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tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
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tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
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tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
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tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
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kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
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kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
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pc, index, kvm_read_c0_guest_entryhi(cop0),
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pc, index, kvm_read_c0_guest_entryhi(cop0),
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@ -866,8 +866,8 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
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tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
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tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
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tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
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tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
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tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
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tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
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tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
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tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
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kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
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kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
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pc, index, kvm_read_c0_guest_entryhi(cop0),
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pc, index, kvm_read_c0_guest_entryhi(cop0),
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@ -2592,7 +2592,7 @@ enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
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}
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}
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} else {
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} else {
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kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
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kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
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tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);
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tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);
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/*
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/*
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* OK we have a Guest TLB entry, now inject it into the
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* OK we have a Guest TLB entry, now inject it into the
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* shadow host TLB
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* shadow host TLB
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@ -141,28 +141,30 @@ int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
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pfn0 = 0;
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pfn0 = 0;
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pfn1 = 0;
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pfn1 = 0;
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} else {
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} else {
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0)
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo[0])
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>> PAGE_SHIFT) < 0)
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>> PAGE_SHIFT) < 0)
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return -1;
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return -1;
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1)
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo[1])
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>> PAGE_SHIFT) < 0)
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>> PAGE_SHIFT) < 0)
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return -1;
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return -1;
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pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0)
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pfn0 = kvm->arch.guest_pmap[
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>> PAGE_SHIFT];
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mips3_tlbpfn_to_paddr(tlb->tlb_lo[0]) >> PAGE_SHIFT];
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pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1)
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pfn1 = kvm->arch.guest_pmap[
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>> PAGE_SHIFT];
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mips3_tlbpfn_to_paddr(tlb->tlb_lo[1]) >> PAGE_SHIFT];
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}
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}
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/* Get attributes from the Guest TLB */
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/* Get attributes from the Guest TLB */
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entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |
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entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |
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(tlb->tlb_lo0 & MIPS3_PG_D) | (tlb->tlb_lo0 & MIPS3_PG_V);
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(tlb->tlb_lo[0] & MIPS3_PG_D) |
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(tlb->tlb_lo[0] & MIPS3_PG_V);
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entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) |
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entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) |
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(tlb->tlb_lo1 & MIPS3_PG_D) | (tlb->tlb_lo1 & MIPS3_PG_V);
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(tlb->tlb_lo[1] & MIPS3_PG_D) |
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(tlb->tlb_lo[1] & MIPS3_PG_V);
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kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,
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kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,
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tlb->tlb_lo0, tlb->tlb_lo1);
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tlb->tlb_lo[0], tlb->tlb_lo[1]);
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preempt_disable();
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preempt_disable();
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entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ?
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entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ?
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@ -86,18 +86,19 @@ void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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tlb = vcpu->arch.guest_tlb[i];
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tlb = vcpu->arch.guest_tlb[i];
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
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(tlb.tlb_lo[0] | tlb.tlb_lo[1]) & MIPS3_PG_V
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? ' ' : '*',
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i, tlb.tlb_hi);
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i, tlb.tlb_hi);
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kvm_info("Lo0=0x%09llx %c%c attr %lx ",
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kvm_info("Lo0=0x%09llx %c%c attr %lx ",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]),
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(tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo[0] & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo[0] & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo0 >> 3) & 7);
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(tlb.tlb_lo[0] >> 3) & 7);
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kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
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kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[1]),
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(tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo[1] & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo[1] & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
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(tlb.tlb_lo[1] >> 3) & 7, tlb.tlb_mask);
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}
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}
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}
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
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EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
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@ -219,7 +220,7 @@ int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
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}
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}
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kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
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kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
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__func__, entryhi, index, tlb[i].tlb_lo0, tlb[i].tlb_lo1);
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__func__, entryhi, index, tlb[i].tlb_lo[0], tlb[i].tlb_lo[1]);
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return index;
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return index;
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}
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}
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