ARM: dts: Zynq DT changes for v5.15

- Enable nand flash controller for ebaz4205 board
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Merge tag 'zynq-dt-for-v5.15' of https://github.com/Xilinx/linux-xlnx into arm/dt

ARM: dts: Zynq DT changes for v5.15

- Enable nand flash controller for ebaz4205 board

* tag 'zynq-dt-for-v5.15' of https://github.com/Xilinx/linux-xlnx:
  ARM: dts: ebaz4205: enable NAND support
  ARM: dts: zynq: add NAND flash controller node

Link: https://lore.kernel.org/r/f3dc69c8-8a22-e938-4ddf-b1052b8c1437@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm/boot/dts/zynq-7000.dtsi

@@ -252,6 +252,27 @@ gem1: ethernet@e000c000 {
 			#size-cells = <0>;
 		};
 
+		smcc: memory-controller@e000e000 {
+			compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+			reg = <0xe000e000 0x0001000>;
+			status = "disabled";
+			clock-names = "memclk", "apb_pclk";
+			clocks = <&clkc 11>, <&clkc 44>;
+			ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+				  0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+				  0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			nfc0: nand-controller@0,0 {
+				compatible = "arm,pl353-nand-r2p1";
+				reg = <0 0 0x1000000>;
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		sdhci0: mmc@e0100000 {
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";

arch/arm/boot/dts/zynq-ebaz4205.dts

@@ -48,6 +48,14 @@ &gpio0 {
 	pinctrl-0 = <&pinctrl_gpio0_default>;
 };
 
+&nfc0 {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+	};
+};
+
 &pinctrl0 {
 	pinctrl_gpio0_default: gpio0-default {
 		mux {
@@ -118,6 +126,10 @@ conf-tx {
 	};
 };
 
+&smcc {
+	status = "okay";
+};
+
 &sdhci0 {
 	status = "okay";
 	disable-wp;