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ARC: [plat-hsdk]: Set initial core pll output frequency 

Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2017-12-09 16:59:15 +03:00 committed by Vineet Gupta
parent c18fc90717
commit a08c832f27
1 changed files with 8 additions and 0 deletions
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8
arch/arc/boot/dts/hsdk.dts
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@ -114,6 +114,14 @@ core_clk: core-clk@0 {
reg = <0x00 0x10>, <0x14B8 0x4>;
#clock-cells = <0>;
clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 1GHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <1000000000>;
};
serial: serial@5000 {