mirror of https://gitee.com/openkylin/linux.git
mmc: sdhci_am654: Add support for input tap delay
DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. With this addition, make sure that DLL is always switched off at the beginning of the set_clock() call to simplify configuration. This also removes the need for the dll_on member in struct sdhci_am654_data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Faiz Abbas
Ulf Hansson
parent
1e753dbb9c
commit
a0a62497f6
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@ -66,6 +66,14 @@
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#define RETRIM_MASK BIT(RETRIM_SHIFT)
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#define SELDLYTXCLK_SHIFT 17
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#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
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#define SELDLYRXCLK_SHIFT 16
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#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
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#define ITAPDLYSEL_SHIFT 0
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#define ITAPDLYSEL_MASK GENMASK(4, 0)
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#define ITAPDLYENA_SHIFT 8
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#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
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#define ITAPCHGWIN_SHIFT 9
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#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
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#define DRIVER_STRENGTH_50_OHM 0x0
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#define DRIVER_STRENGTH_33_OHM 0x1
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@ -73,7 +81,7 @@
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#define DRIVER_STRENGTH_100_OHM 0x3
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#define DRIVER_STRENGTH_40_OHM 0x4
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#define CLOCK_TOO_SLOW_HZ 400000
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#define CLOCK_TOO_SLOW_HZ 50000000
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/* Command Queue Host Controller Interface Base address */
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#define SDHCI_AM654_CQE_BASE_ADDR 0x200
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@ -86,33 +94,55 @@ static struct regmap_config sdhci_am654_regmap_config = {
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};
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struct timing_data {
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const char *binding;
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const char *otap_binding;
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const char *itap_binding;
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u32 capability;
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};
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static const struct timing_data td[] = {
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[MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
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[MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
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[MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
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[MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
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[MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
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[MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
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[MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
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[MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
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"ti,itap-del-sel-legacy",
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0},
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[MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
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"ti,itap-del-sel-mmc-hs",
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MMC_CAP_MMC_HIGHSPEED},
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[MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
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"ti,itap-del-sel-sd-hs",
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MMC_CAP_SD_HIGHSPEED},
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[MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
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"ti,itap-del-sel-sdr12",
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MMC_CAP_UHS_SDR12},
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[MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
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"ti,itap-del-sel-sdr25",
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MMC_CAP_UHS_SDR25},
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[MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
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NULL,
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MMC_CAP_UHS_SDR50},
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[MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
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NULL,
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MMC_CAP_UHS_SDR104},
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[MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
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[MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
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[MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
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[MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
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[MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
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NULL,
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MMC_CAP_UHS_DDR50},
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[MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
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"ti,itap-del-sel-ddr52",
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MMC_CAP_DDR},
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[MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
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NULL,
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MMC_CAP2_HS200},
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[MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
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NULL,
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MMC_CAP2_HS400},
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};
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struct sdhci_am654_data {
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struct regmap *base;
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bool legacy_otapdly;
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int otap_del_sel[ARRAY_SIZE(td)];
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int itap_del_sel[ARRAY_SIZE(td)];
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int clkbuf_sel;
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int trm_icp;
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int drv_strength;
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bool dll_on;
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int strb_sel;
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u32 flags;
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};
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@ -135,6 +165,10 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
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u32 mask, val;
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int ret;
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/* Disable delay chain mode */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
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SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
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if (sdhci_am654->flags & FREQSEL_2_BIT) {
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switch (clock) {
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case 200000000:
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@ -189,8 +223,32 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
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dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
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return;
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}
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}
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sdhci_am654->dll_on = true;
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static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
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u32 itapdly)
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{
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/* Set ITAPCHGWIN before writing to ITAPDLY */
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
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1 << ITAPCHGWIN_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
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itapdly << ITAPDLYSEL_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
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}
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static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
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unsigned char timing)
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{
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u32 mask, val;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
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val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
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mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
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sdhci_am654_write_itapdly(sdhci_am654,
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sdhci_am654->itap_del_sel[timing]);
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}
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static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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@ -202,11 +260,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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u32 otap_del_ena;
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u32 mask, val;
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if (sdhci_am654->dll_on) {
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
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sdhci_am654->dll_on = false;
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}
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regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
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sdhci_set_clock(host, clock);
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@ -234,14 +288,10 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) {
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
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SELDLYTXCLK_MASK, 0);
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if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
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sdhci_am654_setup_dll(host, clock);
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} else {
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
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SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT);
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}
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else
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sdhci_am654_setup_delay_chain(sdhci_am654, timing);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
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sdhci_am654->clkbuf_sel);
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@ -469,7 +519,7 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
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int i;
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int ret;
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ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding,
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ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
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&sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
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if (ret) {
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/*
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@ -492,11 +542,11 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
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for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
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ret = device_property_read_u32(dev, td[i].binding,
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ret = device_property_read_u32(dev, td[i].otap_binding,
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&sdhci_am654->otap_del_sel[i]);
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if (ret) {
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dev_dbg(dev, "Couldn't find %s\n",
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td[i].binding);
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td[i].otap_binding);
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/*
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* Remove the corresponding capability
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* if an otap-del-sel value is not found
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@ -506,6 +556,10 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
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else
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host->mmc->caps2 &= ~td[i].capability;
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}
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if (td[i].itap_binding)
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device_property_read_u32(dev, td[i].itap_binding,
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&sdhci_am654->itap_del_sel[i]);
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}
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return 0;
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