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arm64: dts: qcom: sc7180: Swap order of gpucc and sdhc_2 

Devices are supposed to be sorted by unit address.  These two got
swapped when they landed.  Fix.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200331092832.1.Ic361058ca22d7439164ffea11421740462e14272@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Douglas Anderson 2020-03-31 09:29:00 -07:00 committed by Bjorn Andersson
parent 285aa631e3
commit a0e5aea148
1 changed files with 14 additions and 14 deletions
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28
arch/arm64/boot/dts/qcom/sc7180.dtsi
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@ -1295,6 +1295,20 @@ pinconf-sd-cd {
};
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sc7180-gpucc";
reg = <0 0x05090000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@ -1313,20 +1327,6 @@ sdhc_2: sdhci@8804000 {
status = "disabled";
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sc7180-gpucc";
reg = <0 0x05090000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
qspi: spi@88dc000 {
compatible = "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x600>;