mirror of https://gitee.com/openkylin/linux.git
gpu: host1x: Add Tegra210 support
The host1x unit found in Tegra210 SoCs is very similar to the unit in Tegra124, but it has 2 additional channels for a total of 14 channels. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
e3e70814ce
commit
a134789a67
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@ -10,6 +10,7 @@ host1x-y = \
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mipi.o \
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hw/host1x01.o \
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hw/host1x02.o \
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hw/host1x04.o
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hw/host1x04.o \
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hw/host1x05.o
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obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
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@ -35,6 +35,7 @@
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#include "hw/host1x01.h"
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#include "hw/host1x02.h"
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#include "hw/host1x04.h"
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#include "hw/host1x05.h"
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void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
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{
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@ -87,7 +88,17 @@ static const struct host1x_info host1x04_info = {
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.sync_offset = 0x2100,
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};
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static const struct host1x_info host1x05_info = {
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.nb_channels = 14,
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.nb_pts = 192,
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.nb_mlocks = 16,
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.nb_bases = 64,
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.init = host1x05_init,
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.sync_offset = 0x2100,
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};
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static struct of_device_id host1x_of_match[] = {
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{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
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{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
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{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
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{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
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@ -0,0 +1,42 @@
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/*
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* Host1x init for Tegra210 SoCs
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*
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* Copyright (c) 2015 NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* include hw specification */
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#include "host1x05.h"
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#include "host1x05_hardware.h"
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/* include code */
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#include "cdma_hw.c"
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#include "channel_hw.c"
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#include "debug_hw.c"
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#include "intr_hw.c"
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#include "syncpt_hw.c"
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#include "../dev.h"
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int host1x05_init(struct host1x *host)
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{
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host->channel_op = &host1x_channel_ops;
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host->cdma_op = &host1x_cdma_ops;
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host->cdma_pb_op = &host1x_pushbuffer_ops;
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host->syncpt_op = &host1x_syncpt_ops;
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host->intr_op = &host1x_intr_ops;
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host->debug_op = &host1x_debug_ops;
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return 0;
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}
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@ -0,0 +1,26 @@
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/*
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* Host1x init for Tegra210 SoCs
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*
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* Copyright (c) 2015 NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HOST1X_HOST1X05_H
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#define HOST1X_HOST1X05_H
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struct host1x;
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int host1x05_init(struct host1x *host);
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#endif
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@ -0,0 +1,142 @@
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/*
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* Tegra host1x Register Offsets for Tegra210
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*
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* Copyright (c) 2015 NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HOST1X_HOST1X05_HARDWARE_H
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#define __HOST1X_HOST1X05_HARDWARE_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x05_channel.h"
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#include "hw_host1x05_sync.h"
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#include "hw_host1x05_uclass.h"
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static inline u32 host1x_class_host_wait_syncpt(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_wait_syncpt_indx_f(indx)
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| host1x_uclass_wait_syncpt_thresh_f(threshold);
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}
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static inline u32 host1x_class_host_load_syncpt_base(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_load_syncpt_base_base_indx_f(indx)
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| host1x_uclass_load_syncpt_base_value_f(threshold);
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}
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static inline u32 host1x_class_host_wait_syncpt_base(
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unsigned indx, unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_wait_syncpt_base_indx_f(indx)
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt_base(
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unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_incr_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt(
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unsigned cond, unsigned indx)
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{
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return host1x_uclass_incr_syncpt_cond_f(cond)
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| host1x_uclass_incr_syncpt_indx_f(indx);
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}
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static inline u32 host1x_class_host_indoff_reg_write(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indbe_f(0xf)
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| host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset);
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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static inline u32 host1x_class_host_indoff_reg_read(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset)
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| host1x_uclass_indoff_rwn_read_v();
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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/* cdma opcodes */
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static inline u32 host1x_opcode_setclass(
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unsigned class_id, unsigned offset, unsigned mask)
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{
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
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}
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static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
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{
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return (1 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
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{
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return (2 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
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{
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return (3 << 28) | (offset << 16) | mask;
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}
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static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
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{
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return (4 << 28) | (offset << 16) | value;
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}
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static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
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{
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return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
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host1x_class_host_incr_syncpt(cond, indx));
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}
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static inline u32 host1x_opcode_restart(unsigned address)
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{
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return (5 << 28) | (address >> 4);
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}
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static inline u32 host1x_opcode_gather(unsigned count)
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{
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return (6 << 28) | count;
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}
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static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | count;
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}
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static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
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}
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#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
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#endif
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) 2015 NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef HOST1X_HW_HOST1X05_CHANNEL_H
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#define HOST1X_HW_HOST1X05_CHANNEL_H
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static inline u32 host1x_channel_fifostat_r(void)
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{
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return 0x0;
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}
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#define HOST1X_CHANNEL_FIFOSTAT \
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host1x_channel_fifostat_r()
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static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
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{
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return (r >> 11) & 0x1;
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}
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#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \
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host1x_channel_fifostat_cfempty_v(r)
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static inline u32 host1x_channel_dmastart_r(void)
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{
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return 0x14;
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}
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#define HOST1X_CHANNEL_DMASTART \
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host1x_channel_dmastart_r()
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static inline u32 host1x_channel_dmaput_r(void)
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{
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return 0x18;
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}
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#define HOST1X_CHANNEL_DMAPUT \
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host1x_channel_dmaput_r()
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static inline u32 host1x_channel_dmaget_r(void)
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{
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return 0x1c;
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}
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#define HOST1X_CHANNEL_DMAGET \
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host1x_channel_dmaget_r()
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static inline u32 host1x_channel_dmaend_r(void)
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{
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return 0x20;
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}
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#define HOST1X_CHANNEL_DMAEND \
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host1x_channel_dmaend_r()
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static inline u32 host1x_channel_dmactrl_r(void)
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{
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return 0x24;
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}
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#define HOST1X_CHANNEL_DMACTRL \
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host1x_channel_dmactrl_r()
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static inline u32 host1x_channel_dmactrl_dmastop(void)
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{
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return 1 << 0;
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}
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#define HOST1X_CHANNEL_DMACTRL_DMASTOP \
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host1x_channel_dmactrl_dmastop()
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static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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#define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \
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host1x_channel_dmactrl_dmastop_v(r)
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static inline u32 host1x_channel_dmactrl_dmagetrst(void)
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{
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return 1 << 1;
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}
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#define HOST1X_CHANNEL_DMACTRL_DMAGETRST \
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host1x_channel_dmactrl_dmagetrst()
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static inline u32 host1x_channel_dmactrl_dmainitget(void)
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{
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return 1 << 2;
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}
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#define HOST1X_CHANNEL_DMACTRL_DMAINITGET \
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host1x_channel_dmactrl_dmainitget()
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#endif
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@ -0,0 +1,243 @@
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/*
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* Copyright (c) 2015 NVIDIA Corporation.
|
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*
|
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
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*/
|
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|
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/*
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* Function naming determines intended use:
|
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
|
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* can be |'d with others to produce a full register value for
|
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* register <x>.
|
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
|
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* value can be ~'d and then &'d to clear the value of field <y> for
|
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* register <x>.
|
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
|
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* to place it at field <y> of register <x>. This value can be |'d
|
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* with others to produce a full register value for <x>.
|
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
|
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* This value is suitable for direct comparison with other unshifted
|
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* values appropriate for use in field <y> of register <x>.
|
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
|
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef HOST1X_HW_HOST1X05_SYNC_H
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#define HOST1X_HW_HOST1X05_SYNC_H
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#define REGISTER_STRIDE 4
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static inline u32 host1x_sync_syncpt_r(unsigned int id)
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{
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return 0xf80 + id * REGISTER_STRIDE;
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}
|
||||
#define HOST1X_SYNC_SYNCPT(id) \
|
||||
host1x_sync_syncpt_r(id)
|
||||
static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
|
||||
{
|
||||
return 0xe80 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
|
||||
host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
|
||||
static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
|
||||
{
|
||||
return 0xf00 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
|
||||
host1x_sync_syncpt_thresh_int_disable_r(id)
|
||||
static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
|
||||
{
|
||||
return 0xf20 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
|
||||
host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
|
||||
static inline u32 host1x_sync_cf_setup_r(unsigned int channel)
|
||||
{
|
||||
return 0xc00 + channel * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_CF_SETUP(channel) \
|
||||
host1x_sync_cf_setup_r(channel)
|
||||
static inline u32 host1x_sync_cf_setup_base_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0x3ff;
|
||||
}
|
||||
#define HOST1X_SYNC_CF_SETUP_BASE_V(r) \
|
||||
host1x_sync_cf_setup_base_v(r)
|
||||
static inline u32 host1x_sync_cf_setup_limit_v(u32 r)
|
||||
{
|
||||
return (r >> 16) & 0x3ff;
|
||||
}
|
||||
#define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \
|
||||
host1x_sync_cf_setup_limit_v(r)
|
||||
static inline u32 host1x_sync_cmdproc_stop_r(void)
|
||||
{
|
||||
return 0xac;
|
||||
}
|
||||
#define HOST1X_SYNC_CMDPROC_STOP \
|
||||
host1x_sync_cmdproc_stop_r()
|
||||
static inline u32 host1x_sync_ch_teardown_r(void)
|
||||
{
|
||||
return 0xb0;
|
||||
}
|
||||
#define HOST1X_SYNC_CH_TEARDOWN \
|
||||
host1x_sync_ch_teardown_r()
|
||||
static inline u32 host1x_sync_usec_clk_r(void)
|
||||
{
|
||||
return 0x1a4;
|
||||
}
|
||||
#define HOST1X_SYNC_USEC_CLK \
|
||||
host1x_sync_usec_clk_r()
|
||||
static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
|
||||
{
|
||||
return 0x1a8;
|
||||
}
|
||||
#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
|
||||
host1x_sync_ctxsw_timeout_cfg_r()
|
||||
static inline u32 host1x_sync_ip_busy_timeout_r(void)
|
||||
{
|
||||
return 0x1bc;
|
||||
}
|
||||
#define HOST1X_SYNC_IP_BUSY_TIMEOUT \
|
||||
host1x_sync_ip_busy_timeout_r()
|
||||
static inline u32 host1x_sync_mlock_owner_r(unsigned int id)
|
||||
{
|
||||
return 0x340 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_MLOCK_OWNER(id) \
|
||||
host1x_sync_mlock_owner_r(id)
|
||||
static inline u32 host1x_sync_mlock_owner_chid_v(u32 r)
|
||||
{
|
||||
return (r >> 8) & 0xf;
|
||||
}
|
||||
#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
|
||||
host1x_sync_mlock_owner_chid_v(v)
|
||||
static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r)
|
||||
{
|
||||
return (r >> 1) & 0x1;
|
||||
}
|
||||
#define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \
|
||||
host1x_sync_mlock_owner_cpu_owns_v(r)
|
||||
static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0x1;
|
||||
}
|
||||
#define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \
|
||||
host1x_sync_mlock_owner_ch_owns_v(r)
|
||||
static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
|
||||
{
|
||||
return 0x1380 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
|
||||
host1x_sync_syncpt_int_thresh_r(id)
|
||||
static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
|
||||
{
|
||||
return 0x600 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_BASE(id) \
|
||||
host1x_sync_syncpt_base_r(id)
|
||||
static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
|
||||
{
|
||||
return 0xf60 + id * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
|
||||
host1x_sync_syncpt_cpu_incr_r(id)
|
||||
static inline u32 host1x_sync_cbread_r(unsigned int channel)
|
||||
{
|
||||
return 0xc80 + channel * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_CBREAD(channel) \
|
||||
host1x_sync_cbread_r(channel)
|
||||
static inline u32 host1x_sync_cfpeek_ctrl_r(void)
|
||||
{
|
||||
return 0x74c;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_CTRL \
|
||||
host1x_sync_cfpeek_ctrl_r()
|
||||
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
|
||||
{
|
||||
return (v & 0x3ff) << 0;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
|
||||
host1x_sync_cfpeek_ctrl_addr_f(v)
|
||||
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
|
||||
{
|
||||
return (v & 0xf) << 16;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
|
||||
host1x_sync_cfpeek_ctrl_channr_f(v)
|
||||
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 31;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
|
||||
host1x_sync_cfpeek_ctrl_ena_f(v)
|
||||
static inline u32 host1x_sync_cfpeek_read_r(void)
|
||||
{
|
||||
return 0x750;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_READ \
|
||||
host1x_sync_cfpeek_read_r()
|
||||
static inline u32 host1x_sync_cfpeek_ptrs_r(void)
|
||||
{
|
||||
return 0x754;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_PTRS \
|
||||
host1x_sync_cfpeek_ptrs_r()
|
||||
static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0x3ff;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \
|
||||
host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r)
|
||||
static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
|
||||
{
|
||||
return (r >> 16) & 0x3ff;
|
||||
}
|
||||
#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \
|
||||
host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r)
|
||||
static inline u32 host1x_sync_cbstat_r(unsigned int channel)
|
||||
{
|
||||
return 0xcc0 + channel * REGISTER_STRIDE;
|
||||
}
|
||||
#define HOST1X_SYNC_CBSTAT(channel) \
|
||||
host1x_sync_cbstat_r(channel)
|
||||
static inline u32 host1x_sync_cbstat_cboffset_v(u32 r)
|
||||
{
|
||||
return (r >> 0) & 0xffff;
|
||||
}
|
||||
#define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \
|
||||
host1x_sync_cbstat_cboffset_v(r)
|
||||
static inline u32 host1x_sync_cbstat_cbclass_v(u32 r)
|
||||
{
|
||||
return (r >> 16) & 0x3ff;
|
||||
}
|
||||
#define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \
|
||||
host1x_sync_cbstat_cbclass_v(r)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* Copyright (c) 2015 NVIDIA Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Function naming determines intended use:
|
||||
*
|
||||
* <x>_r(void) : Returns the offset for register <x>.
|
||||
*
|
||||
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
|
||||
*
|
||||
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
|
||||
*
|
||||
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
|
||||
* and masked to place it at field <y> of register <x>. This value
|
||||
* can be |'d with others to produce a full register value for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
|
||||
* value can be ~'d and then &'d to clear the value of field <y> for
|
||||
* register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
|
||||
* to place it at field <y> of register <x>. This value can be |'d
|
||||
* with others to produce a full register value for <x>.
|
||||
*
|
||||
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
|
||||
* <x> value 'r' after being shifted to place its LSB at bit 0.
|
||||
* This value is suitable for direct comparison with other unshifted
|
||||
* values appropriate for use in field <y> of register <x>.
|
||||
*
|
||||
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
|
||||
* field <y> of register <x>. This value is suitable for direct
|
||||
* comparison with unshifted values appropriate for use in field <y>
|
||||
* of register <x>.
|
||||
*/
|
||||
|
||||
#ifndef HOST1X_HW_HOST1X05_UCLASS_H
|
||||
#define HOST1X_HW_HOST1X05_UCLASS_H
|
||||
|
||||
static inline u32 host1x_uclass_incr_syncpt_r(void)
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
#define HOST1X_UCLASS_INCR_SYNCPT \
|
||||
host1x_uclass_incr_syncpt_r()
|
||||
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 8;
|
||||
}
|
||||
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
|
||||
host1x_uclass_incr_syncpt_cond_f(v)
|
||||
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 0;
|
||||
}
|
||||
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
|
||||
host1x_uclass_incr_syncpt_indx_f(v)
|
||||
static inline u32 host1x_uclass_wait_syncpt_r(void)
|
||||
{
|
||||
return 0x8;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT \
|
||||
host1x_uclass_wait_syncpt_r()
|
||||
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 24;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
|
||||
host1x_uclass_wait_syncpt_indx_f(v)
|
||||
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffff) << 0;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
|
||||
host1x_uclass_wait_syncpt_thresh_f(v)
|
||||
static inline u32 host1x_uclass_wait_syncpt_base_r(void)
|
||||
{
|
||||
return 0x9;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
|
||||
host1x_uclass_wait_syncpt_base_r()
|
||||
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 24;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
|
||||
host1x_uclass_wait_syncpt_base_indx_f(v)
|
||||
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 16;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
|
||||
host1x_uclass_wait_syncpt_base_base_indx_f(v)
|
||||
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
|
||||
{
|
||||
return (v & 0xffff) << 0;
|
||||
}
|
||||
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
|
||||
host1x_uclass_wait_syncpt_base_offset_f(v)
|
||||
static inline u32 host1x_uclass_load_syncpt_base_r(void)
|
||||
{
|
||||
return 0xb;
|
||||
}
|
||||
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
|
||||
host1x_uclass_load_syncpt_base_r()
|
||||
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 24;
|
||||
}
|
||||
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
|
||||
host1x_uclass_load_syncpt_base_base_indx_f(v)
|
||||
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffff) << 0;
|
||||
}
|
||||
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
|
||||
host1x_uclass_load_syncpt_base_value_f(v)
|
||||
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 24;
|
||||
}
|
||||
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
|
||||
host1x_uclass_incr_syncpt_base_base_indx_f(v)
|
||||
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
|
||||
{
|
||||
return (v & 0xffffff) << 0;
|
||||
}
|
||||
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
|
||||
host1x_uclass_incr_syncpt_base_offset_f(v)
|
||||
static inline u32 host1x_uclass_indoff_r(void)
|
||||
{
|
||||
return 0x2d;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF \
|
||||
host1x_uclass_indoff_r()
|
||||
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
|
||||
{
|
||||
return (v & 0xf) << 28;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
|
||||
host1x_uclass_indoff_indbe_f(v)
|
||||
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
|
||||
{
|
||||
return (v & 0x1) << 27;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
|
||||
host1x_uclass_indoff_autoinc_f(v)
|
||||
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
|
||||
{
|
||||
return (v & 0xff) << 18;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
|
||||
host1x_uclass_indoff_indmodid_f(v)
|
||||
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
|
||||
{
|
||||
return (v & 0xffff) << 2;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
|
||||
host1x_uclass_indoff_indroffset_f(v)
|
||||
static inline u32 host1x_uclass_indoff_rwn_read_v(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
|
||||
host1x_uclass_indoff_indroffset_f(v)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue