mirror of https://gitee.com/openkylin/linux.git
drm/i915: skylake panel fitting using shared scalers
Enabling skylake panel fitting feature using shared scalers v2: -added force detach parameter for pfit disable purpose (me) -read crtc scaler state from hw state (Daniel) -replaced both skylake_pfit_enable and disable with skylake_pfit_update (me) -added scaler id check to intel_pipe_config_compare (Daniel) v3: -updated function header to kerneldoc format (Matt) -dropped need_scaling checks (Matt) v4: -move clearing of scaler id from commit path to check path (Matt) -updated colorkey checks based on recent updates (me) -squashed scaler check while enabling colorkey to here (me) -use values in plane_state->src as regular integers (me) -changes made not to modify state in commit path (Matt) v5: -squashed helper function to update scaler users to here (Matt) -squashed helper function to detach scaler to here (Matt, me) -changes to align with updated scaler structures (Matt, me) Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chandra Konduru
Daniel Vetter
parent
f76f35dc04
commit
a1b2278e4d
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@ -2931,6 +2931,35 @@ unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
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return i915_gem_obj_ggtt_offset_view(obj, view);
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}
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/*
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* This function detaches (aka. unbinds) unused scalers in hardware
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*/
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void skl_detach_scalers(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev;
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struct drm_i915_private *dev_priv;
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struct intel_crtc_scaler_state *scaler_state;
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int i;
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if (!intel_crtc || !intel_crtc->config)
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return;
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dev = intel_crtc->base.dev;
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dev_priv = dev->dev_private;
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scaler_state = &intel_crtc->config->scaler_state;
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/* loop through and disable scalers that aren't in use */
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for (i = 0; i < intel_crtc->num_scalers; i++) {
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if (!scaler_state->scalers[i].in_use) {
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I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
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I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
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I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
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DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
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intel_crtc->base.base.id, intel_crtc->pipe, i);
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}
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}
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}
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static void skylake_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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@ -4280,16 +4309,175 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
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}
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}
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static void skylake_pfit_enable(struct intel_crtc *crtc)
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/**
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* skl_update_scaler_users - Stages update to crtc's scaler state
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* @intel_crtc: crtc
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* @crtc_state: crtc_state
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* @plane: plane (NULL indicates crtc is requesting update)
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* @plane_state: plane's state
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* @force_detach: request unconditional detachment of scaler
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*
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* This function updates scaler state for requested plane or crtc.
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* To request scaler usage update for a plane, caller shall pass plane pointer.
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* To request scaler usage update for crtc, caller shall pass plane pointer
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* as NULL.
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*
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* Return
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* 0 - scaler_usage updated successfully
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* error - requested scaling cannot be supported or other error condition
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*/
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int
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skl_update_scaler_users(
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struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
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struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
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int force_detach)
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{
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int need_scaling;
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int idx;
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int src_w, src_h, dst_w, dst_h;
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int *scaler_id;
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struct drm_framebuffer *fb;
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struct intel_crtc_scaler_state *scaler_state;
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if (!intel_crtc || !crtc_state)
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return 0;
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scaler_state = &crtc_state->scaler_state;
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idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
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fb = intel_plane ? plane_state->base.fb : NULL;
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if (intel_plane) {
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src_w = drm_rect_width(&plane_state->src) >> 16;
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src_h = drm_rect_height(&plane_state->src) >> 16;
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dst_w = drm_rect_width(&plane_state->dst);
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dst_h = drm_rect_height(&plane_state->dst);
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scaler_id = &plane_state->scaler_id;
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} else {
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struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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src_w = crtc_state->pipe_src_w;
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src_h = crtc_state->pipe_src_h;
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dst_w = adjusted_mode->hdisplay;
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dst_h = adjusted_mode->vdisplay;
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scaler_id = &scaler_state->scaler_id;
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}
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need_scaling = (src_w != dst_w || src_h != dst_h);
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/*
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* if plane is being disabled or scaler is no more required or force detach
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* - free scaler binded to this plane/crtc
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* - in order to do this, update crtc->scaler_usage
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*
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* Here scaler state in crtc_state is set free so that
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* scaler can be assigned to other user. Actual register
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* update to free the scaler is done in plane/panel-fit programming.
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* For this purpose crtc/plane_state->scaler_id isn't reset here.
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*/
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if (force_detach || !need_scaling || (intel_plane &&
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(!fb || !plane_state->visible))) {
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if (*scaler_id >= 0) {
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scaler_state->scaler_users &= ~(1 << idx);
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scaler_state->scalers[*scaler_id].in_use = 0;
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DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
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"crtc_state = %p scaler_users = 0x%x\n",
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intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
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intel_plane ? intel_plane->base.base.id :
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intel_crtc->base.base.id, crtc_state,
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scaler_state->scaler_users);
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*scaler_id = -1;
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}
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return 0;
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}
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/* range checks */
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if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
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dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
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src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
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dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
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DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
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"size is out of scaler range\n",
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intel_plane ? "PLANE" : "CRTC",
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intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
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intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
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return -EINVAL;
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}
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/* check colorkey */
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if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
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DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
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intel_plane->base.base.id);
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return -EINVAL;
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}
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/* Check src format */
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if (intel_plane) {
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switch (fb->pixel_format) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB2101010:
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_XBGR2101010:
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_YVYU:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_VYUY:
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break;
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default:
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DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
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intel_plane->base.base.id, fb->base.id, fb->pixel_format);
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return -EINVAL;
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}
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}
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/* mark this plane as a scaler user in crtc_state */
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scaler_state->scaler_users |= (1 << idx);
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DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
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"crtc_state = %p scaler_users = 0x%x\n",
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intel_plane ? "PLANE" : "CRTC",
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intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
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src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
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return 0;
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}
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static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = crtc->pipe;
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struct intel_crtc_scaler_state *scaler_state =
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&crtc->config->scaler_state;
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DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
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/* To update pfit, first update scaler state */
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skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
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intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
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skl_detach_scalers(crtc);
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if (!enable)
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return;
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if (crtc->config->pch_pfit.enabled) {
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I915_WRITE(PS_CTL(pipe), PS_ENABLE);
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I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
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I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
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int id;
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if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
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DRM_ERROR("Requesting pfit without getting a scaler first\n");
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return;
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}
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id = scaler_state->scaler_id;
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I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
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PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
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I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
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I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
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DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
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}
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}
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@ -4694,7 +4882,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_ddi_enable_pipe_clock(intel_crtc);
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if (IS_SKYLAKE(dev))
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skylake_pfit_enable(intel_crtc);
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skylake_pfit_update(intel_crtc, 1);
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else
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ironlake_pfit_enable(intel_crtc);
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@ -4730,21 +4918,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_crtc_enable_planes(crtc);
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}
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static void skylake_pfit_disable(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = crtc->pipe;
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/* To avoid upsetting the power well on haswell only disable the pfit if
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* it's in use. The hw state code will make sure we get this right. */
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if (crtc->config->pch_pfit.enabled) {
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I915_WRITE(PS_CTL(pipe), 0);
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I915_WRITE(PS_WIN_POS(pipe), 0);
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I915_WRITE(PS_WIN_SZ(pipe), 0);
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}
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}
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static void ironlake_pfit_disable(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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@ -4857,7 +5030,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
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if (IS_SKYLAKE(dev))
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skylake_pfit_disable(intel_crtc);
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skylake_pfit_update(intel_crtc, 0);
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else
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ironlake_pfit_disable(intel_crtc);
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@ -8146,14 +8319,28 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
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uint32_t ps_ctrl = 0;
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int id = -1;
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int i;
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tmp = I915_READ(PS_CTL(crtc->pipe));
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/* find scaler attached to this pipe */
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for (i = 0; i < crtc->num_scalers; i++) {
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ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
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if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
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id = i;
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pipe_config->pch_pfit.enabled = true;
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pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
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pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
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break;
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}
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}
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if (tmp & PS_ENABLE) {
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pipe_config->pch_pfit.enabled = true;
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pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
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pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
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scaler_state->scaler_id = id;
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if (id >= 0) {
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scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
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} else {
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scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
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}
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}
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@ -8787,12 +8974,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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intel_get_pipe_timings(crtc, pipe_config);
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if (INTEL_INFO(dev)->gen >= 9) {
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skl_init_scalers(dev, crtc, pipe_config);
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}
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pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
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if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
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if (IS_SKYLAKE(dev))
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skylake_get_pfit_config(crtc, pipe_config);
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else
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ironlake_get_pfit_config(crtc, pipe_config);
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} else {
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pipe_config->scaler_state.scaler_id = -1;
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pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
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}
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if (IS_HASWELL(dev))
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@ -11320,6 +11514,8 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I(pch_pfit.size);
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}
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PIPE_CONF_CHECK_I(scaler_state.scaler_id);
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/* BDW+ don't expose a synchronous way to read the state */
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if (IS_HASWELL(dev))
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PIPE_CONF_CHECK_I(ips_enabled);
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@ -1351,6 +1351,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
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intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
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adjusted_mode);
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if (INTEL_INFO(dev)->gen >= 9) {
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int ret;
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ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
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if (ret)
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return ret;
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}
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if (!HAS_PCH_SPLIT(dev))
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intel_gmch_panel_fitting(intel_crtc, pipe_config,
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intel_connector->panel.fitting_mode);
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@ -1128,6 +1128,10 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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struct intel_crtc_state *pipe_config);
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void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
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void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
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void skl_detach_scalers(struct intel_crtc *intel_crtc);
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int skl_update_scaler_users(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
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struct intel_plane_state *plane_state, int force_detach);
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unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
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struct drm_i915_gem_object *obj);
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