mirror of https://gitee.com/openkylin/linux.git
ASoC: SOF: Intel: Add Intel specific HDA stream operations
Add support or HDA DSP stream operations for Intel HDA DSPs. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Liam Girdwood
Mark Brown
parent
78ad1f07a4
commit
a1d1e266b4
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@ -0,0 +1,692 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <linux/pm_runtime.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/hda_register.h>
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#include <sound/sof.h>
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#include "../ops.h"
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#include "hda.h"
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/*
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* set up one of BDL entries for a stream
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*/
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static int hda_setup_bdle(struct snd_sof_dev *sdev,
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struct snd_dma_buffer *dmab,
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struct hdac_stream *stream,
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struct sof_intel_dsp_bdl **bdlp,
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int offset, int size, int ioc)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct sof_intel_dsp_bdl *bdl = *bdlp;
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while (size > 0) {
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dma_addr_t addr;
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int chunk;
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if (stream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
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dev_err(sdev->dev, "error: stream frags exceeded\n");
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return -EINVAL;
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}
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addr = snd_sgbuf_get_addr(dmab, offset);
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/* program BDL addr */
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bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
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bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
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/* program BDL size */
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chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
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/* one BDLE should not cross 4K boundary */
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if (bus->align_bdle_4k) {
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u32 remain = 0x1000 - (offset & 0xfff);
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if (chunk > remain)
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chunk = remain;
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}
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bdl->size = cpu_to_le32(chunk);
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/* only program IOC when the whole segment is processed */
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size -= chunk;
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bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
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bdl++;
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stream->frags++;
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offset += chunk;
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dev_vdbg(sdev->dev, "bdl, frags:%d, chunk size:0x%x;\n",
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stream->frags, chunk);
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}
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*bdlp = bdl;
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return offset;
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}
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/*
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* set up Buffer Descriptor List (BDL) for host memory transfer
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* BDL describes the location of the individual buffers and is little endian.
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*/
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int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
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struct snd_dma_buffer *dmab,
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struct hdac_stream *stream)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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struct sof_intel_dsp_bdl *bdl;
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int i, offset, period_bytes, periods;
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int remain, ioc;
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period_bytes = stream->period_bytes;
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dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
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if (!period_bytes)
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period_bytes = stream->bufsize;
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periods = stream->bufsize / period_bytes;
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dev_dbg(sdev->dev, "periods:%d\n", periods);
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remain = stream->bufsize % period_bytes;
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if (remain)
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periods++;
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/* program the initial BDL entries */
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bdl = (struct sof_intel_dsp_bdl *)stream->bdl.area;
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offset = 0;
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stream->frags = 0;
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/*
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* set IOC if don't use position IPC
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* and period_wakeup needed.
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*/
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ioc = hda->no_ipc_position ?
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!stream->no_period_wakeup : 0;
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for (i = 0; i < periods; i++) {
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if (i == (periods - 1) && remain)
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/* set the last small entry */
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offset = hda_setup_bdle(sdev, dmab,
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stream, &bdl, offset,
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remain, 0);
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else
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offset = hda_setup_bdle(sdev, dmab,
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stream, &bdl, offset,
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period_bytes, ioc);
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}
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return offset;
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}
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int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream,
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int enable, u32 size)
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{
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struct hdac_stream *hstream = &stream->hstream;
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u32 mask;
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if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
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dev_err(sdev->dev, "error: address of spib capability is NULL\n");
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return -EINVAL;
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}
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mask = (1 << hstream->index);
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/* enable/disable SPIB for the stream */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
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SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
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enable << hstream->index);
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/* set the SPIB value */
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sof_io_write(sdev, stream->spib_addr, size);
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return 0;
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}
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/* get next unused stream */
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struct hdac_ext_stream *
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hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_ext_stream *stream = NULL;
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struct hdac_stream *s;
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spin_lock_irq(&bus->reg_lock);
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/* get an unused stream */
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list_for_each_entry(s, &bus->stream_list, list) {
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if (s->direction == direction && !s->opened) {
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s->opened = true;
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stream = stream_to_hdac_ext_stream(s);
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break;
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}
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}
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spin_unlock_irq(&bus->reg_lock);
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/* stream found ? */
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if (!stream)
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dev_err(sdev->dev, "error: no free %s streams\n",
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direction == SNDRV_PCM_STREAM_PLAYBACK ?
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"playback" : "capture");
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return stream;
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}
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/* free a stream */
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int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *s;
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spin_lock_irq(&bus->reg_lock);
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/* find used stream */
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list_for_each_entry(s, &bus->stream_list, list) {
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if (s->direction == direction &&
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s->opened && s->stream_tag == stream_tag) {
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s->opened = false;
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spin_unlock_irq(&bus->reg_lock);
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return 0;
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}
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}
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spin_unlock_irq(&bus->reg_lock);
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dev_dbg(sdev->dev, "stream_tag %d not opened!\n", stream_tag);
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return -ENODEV;
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}
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int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream, int cmd)
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{
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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/* cmd must be for audio stream */
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_START:
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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1 << hstream->index,
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1 << hstream->index);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset,
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SOF_HDA_SD_CTL_DMA_START |
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_SD_CTL_DMA_START |
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SOF_HDA_CL_DMA_SD_INT_MASK);
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hstream->running = true;
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_STOP:
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset,
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SOF_HDA_SD_CTL_DMA_START |
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SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset +
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SOF_HDA_ADSP_REG_CL_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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hstream->running = false;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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1 << hstream->index, 0x0);
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break;
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default:
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dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
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return -EINVAL;
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}
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return 0;
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}
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/*
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* prepare for common hdac registers settings, for both code loader
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* and normal stream.
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*/
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int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream,
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struct snd_dma_buffer *dmab,
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struct snd_pcm_hw_params *params)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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int ret, timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
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u32 val, mask;
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if (!stream) {
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dev_err(sdev->dev, "error: no stream available\n");
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return -ENODEV;
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}
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/* decouple host and link DMA */
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mask = 0x1 << hstream->index;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, mask);
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if (!dmab) {
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dev_err(sdev->dev, "error: no dma buffer allocated!\n");
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return -ENODEV;
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}
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/* clear stream status */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
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SOF_HDA_CL_DMA_SD_INT_MASK |
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SOF_HDA_SD_CTL_DMA_START, 0);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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/* stream reset */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
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0x1);
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udelay(3);
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do {
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val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
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sd_offset);
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if (val & 0x1)
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break;
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} while (--timeout);
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if (timeout == 0) {
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dev_err(sdev->dev, "error: stream reset failed\n");
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return -ETIMEDOUT;
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}
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timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
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0x0);
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/* wait for hardware to report that stream is out of reset */
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udelay(3);
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do {
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val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
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sd_offset);
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if ((val & 0x1) == 0)
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break;
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} while (--timeout);
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if (timeout == 0) {
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dev_err(sdev->dev, "error: timeout waiting for stream reset\n");
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return -ETIMEDOUT;
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}
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if (hstream->posbuf)
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*hstream->posbuf = 0;
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/* reset BDL address */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
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0x0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
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0x0);
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/* clear stream status */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
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SOF_HDA_CL_DMA_SD_INT_MASK |
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SOF_HDA_SD_CTL_DMA_START, 0);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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hstream->frags = 0;
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ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
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if (ret < 0) {
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dev_err(sdev->dev, "error: set up of BDL failed\n");
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return ret;
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}
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/* program stream tag to set up stream descriptor for DMA */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
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SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
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hstream->stream_tag <<
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SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
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/* program cyclic buffer length */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
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hstream->bufsize);
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/*
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* Recommended hardware programming sequence for HDAudio DMA format
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*
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* 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
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* for corresponding stream index before the time of writing
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* format to SDxFMT register.
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* 2. Write SDxFMT
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* 3. Set PPCTL.PROCEN bit for corresponding stream index to
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* enable decoupled mode
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*/
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/* couple host and link DMA, disable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, 0);
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/* program stream format */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_CL_SD_FORMAT,
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0xffff, hstream->format_val);
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/* decouple host and link DMA, enable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, mask);
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/* program last valid index */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
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0xffff, (hstream->frags - 1));
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/* program BDL address */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
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(u32)hstream->bdl.addr);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
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upper_32_bits(hstream->bdl.addr));
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/* enable position buffer */
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if (!(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
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& SOF_HDA_ADSP_DPLBASE_ENABLE)) {
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
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upper_32_bits(bus->posbuf.addr));
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
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(u32)bus->posbuf.addr |
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SOF_HDA_ADSP_DPLBASE_ENABLE);
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}
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/* set interrupt enable bits */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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/* read FIFO size */
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if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
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hstream->fifo_size =
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snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
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hstream->fifo_size &= 0xffff;
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hstream->fifo_size += 1;
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} else {
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hstream->fifo_size = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
irqreturn_t hda_dsp_stream_interrupt(int irq, void *context)
|
||||
{
|
||||
struct hdac_bus *bus = context;
|
||||
u32 status;
|
||||
|
||||
if (!pm_runtime_active(bus->dev))
|
||||
return IRQ_NONE;
|
||||
|
||||
spin_lock(&bus->reg_lock);
|
||||
|
||||
status = snd_hdac_chip_readl(bus, INTSTS);
|
||||
if (status == 0 || status == 0xffffffff) {
|
||||
spin_unlock(&bus->reg_lock);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
/* clear rirb int */
|
||||
status = snd_hdac_chip_readb(bus, RIRBSTS);
|
||||
if (status & RIRB_INT_MASK) {
|
||||
if (status & RIRB_INT_RESPONSE)
|
||||
snd_hdac_bus_update_rirb(bus);
|
||||
snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
spin_unlock(&bus->reg_lock);
|
||||
|
||||
return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
|
||||
}
|
||||
|
||||
irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
|
||||
{
|
||||
struct hdac_bus *bus = context;
|
||||
struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
|
||||
struct hdac_stream *s;
|
||||
u32 status = snd_hdac_chip_readl(bus, INTSTS);
|
||||
u32 sd_status;
|
||||
|
||||
/* check streams */
|
||||
list_for_each_entry(s, &bus->stream_list, list) {
|
||||
if (status & (1 << s->index) && s->opened) {
|
||||
sd_status = snd_hdac_stream_readb(s, SD_STS);
|
||||
|
||||
dev_vdbg(bus->dev, "stream %d status 0x%x\n",
|
||||
s->index, sd_status);
|
||||
|
||||
snd_hdac_stream_writeb(s, SD_STS, SD_INT_MASK);
|
||||
|
||||
if (!s->substream ||
|
||||
!s->running ||
|
||||
(sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
|
||||
continue;
|
||||
|
||||
/* Inform ALSA only in case not do that with IPC */
|
||||
if (sof_hda->no_ipc_position)
|
||||
snd_pcm_period_elapsed(s->substream);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int hda_dsp_stream_init(struct snd_sof_dev *sdev)
|
||||
{
|
||||
struct hdac_bus *bus = sof_to_bus(sdev);
|
||||
struct hdac_ext_stream *stream;
|
||||
struct hdac_stream *hstream;
|
||||
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
||||
int sd_offset;
|
||||
int i, num_playback, num_capture, num_total, ret;
|
||||
u32 gcap;
|
||||
|
||||
gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
|
||||
dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
|
||||
|
||||
/* get stream count from GCAP */
|
||||
num_capture = (gcap >> 8) & 0x0f;
|
||||
num_playback = (gcap >> 12) & 0x0f;
|
||||
num_total = num_playback + num_capture;
|
||||
|
||||
dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
|
||||
num_playback, num_capture);
|
||||
|
||||
if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
|
||||
dev_err(sdev->dev, "error: too many playback streams %d\n",
|
||||
num_playback);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
|
||||
dev_err(sdev->dev, "error: too many capture streams %d\n",
|
||||
num_playback);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* mem alloc for the position buffer
|
||||
* TODO: check position buffer update
|
||||
*/
|
||||
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
|
||||
SOF_HDA_DPIB_ENTRY_SIZE * num_total,
|
||||
&bus->posbuf);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
/* mem alloc for the CORB/RIRB ringbuffers */
|
||||
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
|
||||
PAGE_SIZE, &bus->rb);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: RB alloc failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* create capture streams */
|
||||
for (i = 0; i < num_capture; i++) {
|
||||
struct sof_intel_hda_stream *hda_stream;
|
||||
|
||||
hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
|
||||
GFP_KERNEL);
|
||||
if (!hda_stream)
|
||||
return -ENOMEM;
|
||||
|
||||
stream = &hda_stream->hda_stream;
|
||||
|
||||
stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
|
||||
SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
|
||||
|
||||
stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
|
||||
SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
|
||||
SOF_HDA_PPLC_INTERVAL * i;
|
||||
|
||||
/* do we support SPIB */
|
||||
if (sdev->bar[HDA_DSP_SPIB_BAR]) {
|
||||
stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
|
||||
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
|
||||
SOF_HDA_SPIB_SPIB;
|
||||
|
||||
stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
|
||||
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
|
||||
SOF_HDA_SPIB_MAXFIFO;
|
||||
}
|
||||
|
||||
hstream = &stream->hstream;
|
||||
hstream->bus = bus;
|
||||
hstream->sd_int_sta_mask = 1 << i;
|
||||
hstream->index = i;
|
||||
sd_offset = SOF_STREAM_SD_OFFSET(hstream);
|
||||
hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
|
||||
hstream->stream_tag = i + 1;
|
||||
hstream->opened = false;
|
||||
hstream->running = false;
|
||||
hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
|
||||
|
||||
/* memory alloc for stream BDL */
|
||||
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
|
||||
HDA_DSP_BDL_SIZE, &hstream->bdl);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
hstream->posbuf = (__le32 *)(bus->posbuf.area +
|
||||
(hstream->index) * 8);
|
||||
|
||||
list_add_tail(&hstream->list, &bus->stream_list);
|
||||
}
|
||||
|
||||
/* create playback streams */
|
||||
for (i = num_capture; i < num_total; i++) {
|
||||
struct sof_intel_hda_stream *hda_stream;
|
||||
|
||||
hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
|
||||
GFP_KERNEL);
|
||||
if (!hda_stream)
|
||||
return -ENOMEM;
|
||||
|
||||
stream = &hda_stream->hda_stream;
|
||||
|
||||
/* we always have DSP support */
|
||||
stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
|
||||
SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
|
||||
|
||||
stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
|
||||
SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
|
||||
SOF_HDA_PPLC_INTERVAL * i;
|
||||
|
||||
/* do we support SPIB */
|
||||
if (sdev->bar[HDA_DSP_SPIB_BAR]) {
|
||||
stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
|
||||
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
|
||||
SOF_HDA_SPIB_SPIB;
|
||||
|
||||
stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
|
||||
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
|
||||
SOF_HDA_SPIB_MAXFIFO;
|
||||
}
|
||||
|
||||
hstream = &stream->hstream;
|
||||
hstream->bus = bus;
|
||||
hstream->sd_int_sta_mask = 1 << i;
|
||||
hstream->index = i;
|
||||
sd_offset = SOF_STREAM_SD_OFFSET(hstream);
|
||||
hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
|
||||
hstream->stream_tag = i - num_capture + 1;
|
||||
hstream->opened = false;
|
||||
hstream->running = false;
|
||||
hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
|
||||
|
||||
/* mem alloc for stream BDL */
|
||||
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
|
||||
HDA_DSP_BDL_SIZE, &hstream->bdl);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
hstream->posbuf = (__le32 *)(bus->posbuf.area +
|
||||
(hstream->index) * 8);
|
||||
|
||||
list_add_tail(&hstream->list, &bus->stream_list);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hda_dsp_stream_free(struct snd_sof_dev *sdev)
|
||||
{
|
||||
struct hdac_bus *bus = sof_to_bus(sdev);
|
||||
struct hdac_stream *s, *_s;
|
||||
struct hdac_ext_stream *stream;
|
||||
struct sof_intel_hda_stream *hda_stream;
|
||||
|
||||
/* free position buffer */
|
||||
if (bus->posbuf.area)
|
||||
snd_dma_free_pages(&bus->posbuf);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
/* free position buffer */
|
||||
if (bus->rb.area)
|
||||
snd_dma_free_pages(&bus->rb);
|
||||
#endif
|
||||
|
||||
list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
|
||||
/* TODO: decouple */
|
||||
|
||||
/* free bdl buffer */
|
||||
if (s->bdl.area)
|
||||
snd_dma_free_pages(&s->bdl);
|
||||
list_del(&s->list);
|
||||
stream = stream_to_hdac_ext_stream(s);
|
||||
hda_stream = container_of(stream, struct sof_intel_hda_stream,
|
||||
hda_stream);
|
||||
devm_kfree(sdev->dev, hda_stream);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue