mirror of https://gitee.com/openkylin/linux.git
Qualcomm ARM64 Updates for v4.14 Part 2
* Add IPQ8074 SoC and HK01 board support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZl1PKAAoJEFKiBbHx2RXVq40QAIoFRYmWBywq/UquEf0qH6UF y7Y0Ig7ba6lXLhKJlUx8bQYXtU97CLDuJXw9pIvh8IxPZmYKWQd9zG3FfZZIaRSf /zN9SDBZV7Q8JyZXL7u1GCxFC4bouhc6L9n8ttYUGjeiYh4Xq2ZqwOL+YAQhnSQn UuYS3eb21/0rCZmWzkdOU7rYSutkhhaCtRWh9QcndZKoOquvnvQgWlVkOELnTbND 4kc2txOJ8juRnzwpvlfYsOnFet4XQC/RCz1vGSgu3ljXCC5rTYMKd7AstHnsAc2x NNJCyi0fdMEbPSAvI3nK7fFinS8rppKfNmAG4T4UjmAtu19wCKmlPblRYhIgZwk9 YngZh2FbHLSdV/rDJG4E6UoktvV+PeRlajTZofT0su4wLJPxFiTTZWlOPmg/Y9Gf dVBw+FRFJRj2L4gu5n+8pKvsQsc9zAv1h+YMJoVRv8Zz45M9QoihPMapAjwDu2hz PtCSjKO9ebnl6J8GpI3FaKtzjywLCG12/xp+6NUmSa8lz6sxkTPFwcgRU4Dm+bj6 xa8Tt63lz/rEfuOBj/+niadSh/mATEiOvUlt0AEVNt/JfjOIxq/s0FDpGwYzJRFE z63TvqNZ7V+irEweJPmkyvMR2huqYHo32FqGkXkZQIIyUHzEnnQJWJn3D1wmhYWX btJBe1OV0SKm9+xc8XwY =JCl4 -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Pull "Qualcomm ARM64 Updates for v4.14 Part 2" from Andy Gross: * Add IPQ8074 SoC and HK01 board support * tag 'qcom-arm64-for-4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: Add ipq8074 SoC and HK01 board support
This commit is contained in:
Arnd Bergmann
commit
a282ac2d41
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@ -1,5 +1,6 @@
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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@ -0,0 +1,52 @@
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/dts-v1/;
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/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "ipq8074.dtsi"
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
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compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &blsp1_uart5;
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};
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chosen {
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stdout-path = "serial0";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x20000000>;
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};
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soc {
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pinctrl@1000000 {
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serial_4_pins: serial4_pinmux {
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mux {
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pins = "gpio23", "gpio24";
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function = "blsp4_uart1";
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bias-disable;
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};
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};
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};
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serial@78b3000 {
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pinctrl-0 = <&serial_4_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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};
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};
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@ -0,0 +1,194 @@
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ8074";
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compatible = "qcom,ipq8074";
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soc: soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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pinctrl@1000000 {
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compatible = "qcom,ipq8074-pinctrl";
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reg = <0x1000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb121000 0x1000>,
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<0xb122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb128000 0x1000>;
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status = "disabled";
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};
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};
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq8074";
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reg = <0x1800000 0x80000>;
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#clock-cells = <0x1>;
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#reset-cells = <0x1>;
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};
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blsp1_uart5: serial@78b3000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b3000 0x200>;
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interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <0x2>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
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};
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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#clock-cells = <0>;
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};
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};
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};
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