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drm/i915/icl: Add register definition for DFLEXDPMLE
DFLEXDPMLE register is required to tell the FIA hardware which main links of DP are enabled on TCC Connectors. FIA uses this information to program PHY to Controller signal mapping. This register is applicable in both TC connector's Alternate mode as well as DP connector mode. v2: * Remove _ICL prefix since the reg is first introduced in ICL (Paulo) * s/ICL/icl in commit message (Lucas) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1527275032-4555-1-git-send-email-manasi.d.navare@intel.com
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@ -1990,6 +1990,11 @@ enum i915_power_well_id {
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_ICL_PORT_COMP_DW10_A, \
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_ICL_PORT_COMP_DW10_B)
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/* ICL PHY DFLEX registers */
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#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
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#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
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#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
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/* BXT PHY Ref registers */
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#define _PORT_REF_DW3_A 0x16218C
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#define _PORT_REF_DW3_BC 0x6C18C
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