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mmc: dw_mmc: make IO accessors endian agnostic 

The dw_mmc driver does not use endian agnostic IO accessors, so fix
the use of __raw reads and writes to be the relaxed versions.

This fixes the dw_mmc driver initialisation on Altera socfpga in big endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ben Dooks 2015-03-25 11:27:50 +00:00 committed by Ulf Hansson
parent f5c5179b9a
commit a2f17680f4
1 changed files with 6 additions and 6 deletions
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12
drivers/mmc/host/dw_mmc.h
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@ -171,22 +171,22 @@
/* Register access macros */ /* Register access macros */
#define mci_readl(dev, reg) \ #define mci_readl(dev, reg) \
__raw_readl((dev)->regs + SDMMC_##reg) readl_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writel(dev, reg, value) \ #define mci_writel(dev, reg, value) \
__raw_writel((value), (dev)->regs + SDMMC_##reg) writel_relaxed((value), (dev)->regs + SDMMC_##reg)
/* 16-bit FIFO access macros */ /* 16-bit FIFO access macros */
#define mci_readw(dev, reg) \ #define mci_readw(dev, reg) \
__raw_readw((dev)->regs + SDMMC_##reg) readw_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writew(dev, reg, value) \ #define mci_writew(dev, reg, value) \
__raw_writew((value), (dev)->regs + SDMMC_##reg) writew_relaxed((value), (dev)->regs + SDMMC_##reg)
/* 64-bit FIFO access macros */ /* 64-bit FIFO access macros */
#ifdef readq #ifdef readq
#define mci_readq(dev, reg) \ #define mci_readq(dev, reg) \
__raw_readq((dev)->regs + SDMMC_##reg) readq_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writeq(dev, reg, value) \ #define mci_writeq(dev, reg, value) \
__raw_writeq((value), (dev)->regs + SDMMC_##reg) writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
#else #else
/* /*
* Dummy readq implementation for architectures that don't define it. * Dummy readq implementation for architectures that don't define it.