mirror of https://gitee.com/openkylin/linux.git
irqchip updates for Linux 5.1
- Core pseudo-NMI handling code - Allow the default irq domain to be retrieved - A new interrupt controller for the Loongson LS1X platform - Affinity support for the SiFive PLIC - Better support for the iMX irqsteer driver - NUMA aware memory allocations for GICv3 - A handful of other fixes (i8259, GICv3, PLIC) -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlxwGtgVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpD+2YP/2m9cVU3Z9ak8+HdSblq2Sw8QPfd RshYS+DzppLUzhzj2w2jnz9eP2fWEqBwrQmvtOI8Fo+id0PvdE3ngaP4hPMJDyuU Ou02TV6YwE4jknoO02RXOdeBJArccc1WR5++YZjp1gGUABFUPCHwKLoZgysurapV sZQ1Ten3wlsrZKKNTdWfYFWB36d7J3eqFYeGy3sll1wQ6XUbHmUJPPrSfXMqDYzY giDD/DH8IIhfnRs+T2TxGzKtTDMnJRYJYQK2bNgtNAW+wEY2BtCLSHj8//3bK0R9 Jek9xg1NLpbQE+T8f2ZUd6BjbVxmDd3mGPvshXKyHFESl4fvC9yrddC86dBzHwrN VJmaES974PBuMtE2xPZGInh77EcelVC7OPeXsnjVMrUZo0s7tFY/TWA+rqCOLmgC A+0jagCDx1nTTYGXsqoyrHThoQoYZRX6AnXFeDJb9OLo3cV7x4w/FPORstM0PbAc butyZulVg1YQ+Y+oJK/UvIkdFL7FFqB/kgZK/lrL0InvbQMj4CBt3bsWY5OxgInF E02tgzEnrx1nHGi1XPnCTOs7DnKeaPR/h/u3PjoT7FeiZLClyiGDw7V/NuF+buLB w7Pqpn835CnkXC27MycTjPo23eZv690M4vcHL4vrhN+iuGp+2hZdXUiR15mZnH6m g0N8anZbL1iol0Gm =M6YA -----END PGP SIGNATURE----- Merge tag 'irqchip-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier - Core pseudo-NMI handling code - Allow the default irq domain to be retrieved - A new interrupt controller for the Loongson LS1X platform - Affinity support for the SiFive PLIC - Better support for the iMX irqsteer driver - NUMA aware memory allocations for GICv3 - A handful of other fixes (i8259, GICv3, PLIC)
This commit is contained in:
Thomas Gleixner
commit
a324ca9cad
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@ -6,8 +6,9 @@ Required properties:
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- "fsl,imx8m-irqsteer"
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- "fsl,imx-irqsteer"
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- reg: Physical base address and size of registers.
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- interrupts: Should contain the parent interrupt line used to multiplex the
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input interrupts.
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- interrupts: Should contain the up to 8 parent interrupt lines used to
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multiplex the input interrupts. They should be specified sequentially
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from output 0 to 7.
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- clocks: Should contain one clock for entry in clock-names
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see Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names:
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@ -16,8 +17,8 @@ Required properties:
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- fsl,channel: The output channel that all input IRQs should be steered into.
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- fsl,irq-groups: Number of IRQ groups managed by this controller instance.
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Each group manages 64 input interrupts.
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- fsl,num-irqs: Number of input interrupts of this channel.
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Should be multiple of 32 input interrupts and up to 512 interrupts.
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Example:
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@ -28,7 +29,7 @@ Example:
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
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clock-names = "ipg";
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fsl,channel = <0>;
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fsl,irq-groups = <1>;
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fsl,num-irqs = <64>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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@ -0,0 +1,24 @@
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Loongson ls1x Interrupt Controller
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Required properties:
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- compatible : should be "loongson,ls1x-intc". Valid strings are:
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 2.
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- interrupts : Specifies the CPU interrupt the controller is connected to.
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Example:
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intc: interrupt-controller@1fd01040 {
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compatible = "loongson,ls1x-intc";
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reg = <0x1fd01040 0x18>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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@ -406,6 +406,15 @@ config IMX_IRQSTEER
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help
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Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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default y
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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help
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Support for the Loongson-1 platform Interrupt Controller.
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endmenu
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config SIFIVE_PLIC
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@ -94,3 +94,4 @@ obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
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obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
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@ -129,8 +129,9 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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unsigned long flags;
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irq_gc_lock(gc);
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irq_gc_lock_irqsave(gc, flags);
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/* Save the current mask */
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b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
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@ -139,7 +140,7 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
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irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
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irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
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}
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irq_gc_unlock(gc);
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irq_gc_unlock_irqrestore(gc, flags);
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}
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static void brcmstb_l2_intc_resume(struct irq_data *d)
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@ -147,8 +148,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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unsigned long flags;
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irq_gc_lock(gc);
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irq_gc_lock_irqsave(gc, flags);
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if (ct->chip.irq_ack) {
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/* Clear unmasked non-wakeup interrupts */
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irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
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@ -158,7 +160,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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/* Restore the saved mask */
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irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
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irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
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irq_gc_unlock(gc);
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irq_gc_unlock_irqrestore(gc, flags);
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}
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static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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@ -1737,6 +1737,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
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u64 type = GITS_BASER_TYPE(val);
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u64 baser_phys, tmp;
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u32 alloc_pages;
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struct page *page;
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void *base;
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retry_alloc_baser:
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@ -1749,10 +1750,11 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
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order = get_order(GITS_BASER_PAGES_MAX * psz);
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}
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base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (!base)
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
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if (!page)
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return -ENOMEM;
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base = (void *)page_address(page);
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baser_phys = virt_to_phys(base);
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/* Check if the physical address of the memory is above 48bits */
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@ -1946,6 +1948,8 @@ static int its_alloc_tables(struct its_node *its)
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indirect = its_parse_indirect_baser(its, baser,
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psz, &order,
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its->device_ids);
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break;
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case GITS_BASER_TYPE_VCPU:
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indirect = its_parse_indirect_baser(its, baser,
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psz, &order,
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@ -2236,7 +2240,8 @@ static struct its_baser *its_get_baser(struct its_node *its, u32 type)
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return NULL;
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}
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static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
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static bool its_alloc_table_entry(struct its_node *its,
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struct its_baser *baser, u32 id)
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{
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struct page *page;
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u32 esz, idx;
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@ -2256,7 +2261,8 @@ static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
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/* Allocate memory for 2nd level table */
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if (!table[idx]) {
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page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
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get_order(baser->psz));
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if (!page)
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return false;
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@ -2287,7 +2293,7 @@ static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
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if (!baser)
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return (ilog2(dev_id) < its->device_ids);
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return its_alloc_table_entry(baser, dev_id);
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return its_alloc_table_entry(its, baser, dev_id);
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}
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static bool its_alloc_vpe_table(u32 vpe_id)
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@ -2311,7 +2317,7 @@ static bool its_alloc_vpe_table(u32 vpe_id)
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if (!baser)
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return false;
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if (!its_alloc_table_entry(baser, vpe_id))
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if (!its_alloc_table_entry(its, baser, vpe_id))
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return false;
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}
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@ -2345,7 +2351,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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nr_ites = max(2, nvecs);
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sz = nr_ites * its->ite_size;
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sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
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itt = kzalloc(sz, GFP_KERNEL);
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itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
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if (alloc_lpis) {
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lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
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if (lpi_map)
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@ -3487,6 +3493,7 @@ static int __init its_probe_one(struct resource *res,
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void __iomem *its_base;
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u32 val, ctlr;
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u64 baser, tmp, typer;
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struct page *page;
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int err;
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its_base = ioremap(res->start, resource_size(res));
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@ -3542,12 +3549,13 @@ static int __init its_probe_one(struct resource *res,
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its->numa_node = numa_node;
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its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
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get_order(ITS_CMD_QUEUE_SZ));
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if (!its->cmd_base) {
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
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get_order(ITS_CMD_QUEUE_SZ));
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if (!page) {
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err = -ENOMEM;
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goto out_free_its;
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}
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its->cmd_base = (void *)page_address(page);
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its->cmd_write = its->cmd_base;
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its->fwnode_handle = handle;
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its->get_msi_base = its_irq_get_msi_base;
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@ -225,14 +225,6 @@ static struct syscore_ops i8259_syscore_ops = {
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.shutdown = i8259A_shutdown,
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};
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static int __init i8259A_init_sysfs(void)
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{
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register_syscore_ops(&i8259_syscore_ops);
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return 0;
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}
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device_initcall(i8259A_init_sysfs);
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static void init_8259A(int auto_eoi)
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{
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unsigned long flags;
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@ -332,6 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
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panic("Failed to add i8259 IRQ domain");
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setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
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register_syscore_ops(&i8259_syscore_ops);
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return domain;
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}
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|
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@ -10,10 +10,11 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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#define CTRL_STRIDE_OFF(_t, _r) (_t * 8 * _r)
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#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
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#define CHANCTRL 0x0
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#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
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#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
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@ -21,12 +22,15 @@
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#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
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#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
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#define CHAN_MAX_OUTPUT_INT 0x8
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struct irqsteer_data {
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void __iomem *regs;
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struct clk *ipg_clk;
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int irq;
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int irq[CHAN_MAX_OUTPUT_INT];
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int irq_count;
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raw_spinlock_t lock;
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int irq_groups;
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int reg_num;
|
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int channel;
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struct irq_domain *domain;
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u32 *saved_reg;
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|
|
@ -35,7 +39,7 @@ struct irqsteer_data {
|
|||
static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
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unsigned long irqnum)
|
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{
|
||||
return (data->irq_groups * 2 - irqnum / 32 - 1);
|
||||
return (data->reg_num - irqnum / 32 - 1);
|
||||
}
|
||||
|
||||
static void imx_irqsteer_irq_unmask(struct irq_data *d)
|
||||
|
|
@ -46,9 +50,9 @@ static void imx_irqsteer_irq_unmask(struct irq_data *d)
|
|||
u32 val;
|
||||
|
||||
raw_spin_lock_irqsave(&data->lock, flags);
|
||||
val = readl_relaxed(data->regs + CHANMASK(idx, data->irq_groups));
|
||||
val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
|
||||
val |= BIT(d->hwirq % 32);
|
||||
writel_relaxed(val, data->regs + CHANMASK(idx, data->irq_groups));
|
||||
writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
|
||||
raw_spin_unlock_irqrestore(&data->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -60,9 +64,9 @@ static void imx_irqsteer_irq_mask(struct irq_data *d)
|
|||
u32 val;
|
||||
|
||||
raw_spin_lock_irqsave(&data->lock, flags);
|
||||
val = readl_relaxed(data->regs + CHANMASK(idx, data->irq_groups));
|
||||
val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
|
||||
val &= ~BIT(d->hwirq % 32);
|
||||
writel_relaxed(val, data->regs + CHANMASK(idx, data->irq_groups));
|
||||
writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
|
||||
raw_spin_unlock_irqrestore(&data->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -87,23 +91,47 @@ static const struct irq_domain_ops imx_irqsteer_domain_ops = {
|
|||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < data->irq_count; i++) {
|
||||
if (data->irq[i] == irq)
|
||||
return i * 64;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void imx_irqsteer_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irqsteer_data *data = irq_desc_get_handler_data(desc);
|
||||
int i;
|
||||
int hwirq;
|
||||
int irq, i;
|
||||
|
||||
chained_irq_enter(irq_desc_get_chip(desc), desc);
|
||||
|
||||
for (i = 0; i < data->irq_groups * 64; i += 32) {
|
||||
int idx = imx_irqsteer_get_reg_index(data, i);
|
||||
irq = irq_desc_get_irq(desc);
|
||||
hwirq = imx_irqsteer_get_hwirq_base(data, irq);
|
||||
if (hwirq < 0) {
|
||||
pr_warn("%s: unable to get hwirq base for irq %d\n",
|
||||
__func__, irq);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < 2; i++, hwirq += 32) {
|
||||
int idx = imx_irqsteer_get_reg_index(data, hwirq);
|
||||
unsigned long irqmap;
|
||||
int pos, virq;
|
||||
|
||||
if (hwirq >= data->reg_num * 32)
|
||||
break;
|
||||
|
||||
irqmap = readl_relaxed(data->regs +
|
||||
CHANSTATUS(idx, data->irq_groups));
|
||||
CHANSTATUS(idx, data->reg_num));
|
||||
|
||||
for_each_set_bit(pos, &irqmap, 32) {
|
||||
virq = irq_find_mapping(data->domain, pos + i);
|
||||
virq = irq_find_mapping(data->domain, pos + hwirq);
|
||||
if (virq)
|
||||
generic_handle_irq(virq);
|
||||
}
|
||||
|
|
@ -117,7 +145,8 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
struct device_node *np = pdev->dev.of_node;
|
||||
struct irqsteer_data *data;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
u32 irqs_num;
|
||||
int i, ret;
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
|
|
@ -130,12 +159,6 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(data->regs);
|
||||
}
|
||||
|
||||
data->irq = platform_get_irq(pdev, 0);
|
||||
if (data->irq <= 0) {
|
||||
dev_err(&pdev->dev, "failed to get irq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
||||
if (IS_ERR(data->ipg_clk)) {
|
||||
ret = PTR_ERR(data->ipg_clk);
|
||||
|
|
@ -146,12 +169,19 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
|
||||
raw_spin_lock_init(&data->lock);
|
||||
|
||||
of_property_read_u32(np, "fsl,irq-groups", &data->irq_groups);
|
||||
of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
|
||||
of_property_read_u32(np, "fsl,channel", &data->channel);
|
||||
|
||||
/*
|
||||
* There is one output irq for each group of 64 inputs.
|
||||
* One register bit map can represent 32 input interrupts.
|
||||
*/
|
||||
data->irq_count = DIV_ROUND_UP(irqs_num, 64);
|
||||
data->reg_num = irqs_num / 32;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP)) {
|
||||
data->saved_reg = devm_kzalloc(&pdev->dev,
|
||||
sizeof(u32) * data->irq_groups * 2,
|
||||
sizeof(u32) * data->reg_num,
|
||||
GFP_KERNEL);
|
||||
if (!data->saved_reg)
|
||||
return -ENOMEM;
|
||||
|
|
@ -166,27 +196,48 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
|||
/* steer all IRQs into configured channel */
|
||||
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
|
||||
|
||||
data->domain = irq_domain_add_linear(np, data->irq_groups * 64,
|
||||
data->domain = irq_domain_add_linear(np, data->reg_num * 32,
|
||||
&imx_irqsteer_domain_ops, data);
|
||||
if (!data->domain) {
|
||||
dev_err(&pdev->dev, "failed to create IRQ domain\n");
|
||||
clk_disable_unprepare(data->ipg_clk);
|
||||
return -ENOMEM;
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(data->irq, imx_irqsteer_irq_handler,
|
||||
data);
|
||||
if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < data->irq_count; i++) {
|
||||
data->irq[i] = irq_of_parse_and_map(np, i);
|
||||
if (!data->irq[i]) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(data->irq[i],
|
||||
imx_irqsteer_irq_handler,
|
||||
data);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
clk_disable_unprepare(data->ipg_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int imx_irqsteer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < irqsteer_data->irq_count; i++)
|
||||
irq_set_chained_handler_and_data(irqsteer_data->irq[i],
|
||||
NULL, NULL);
|
||||
|
||||
irq_set_chained_handler_and_data(irqsteer_data->irq, NULL, NULL);
|
||||
irq_domain_remove(irqsteer_data->domain);
|
||||
|
||||
clk_disable_unprepare(irqsteer_data->ipg_clk);
|
||||
|
|
@ -199,9 +250,9 @@ static void imx_irqsteer_save_regs(struct irqsteer_data *data)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < data->irq_groups * 2; i++)
|
||||
for (i = 0; i < data->reg_num; i++)
|
||||
data->saved_reg[i] = readl_relaxed(data->regs +
|
||||
CHANMASK(i, data->irq_groups));
|
||||
CHANMASK(i, data->reg_num));
|
||||
}
|
||||
|
||||
static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
|
||||
|
|
@ -209,9 +260,9 @@ static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
|
|||
int i;
|
||||
|
||||
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
|
||||
for (i = 0; i < data->irq_groups * 2; i++)
|
||||
for (i = 0; i < data->reg_num; i++)
|
||||
writel_relaxed(data->saved_reg[i],
|
||||
data->regs + CHANMASK(i, data->irq_groups));
|
||||
data->regs + CHANMASK(i, data->reg_num));
|
||||
}
|
||||
|
||||
static int imx_irqsteer_suspend(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019, Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
* Loongson-1 platform IRQ support
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
|
||||
#define LS_REG_INTC_STATUS 0x00
|
||||
#define LS_REG_INTC_EN 0x04
|
||||
#define LS_REG_INTC_SET 0x08
|
||||
#define LS_REG_INTC_CLR 0x0c
|
||||
#define LS_REG_INTC_POL 0x10
|
||||
#define LS_REG_INTC_EDGE 0x14
|
||||
|
||||
/**
|
||||
* struct ls1x_intc_priv - private ls1x-intc data.
|
||||
* @domain: IRQ domain.
|
||||
* @intc_base: IO Base of intc registers.
|
||||
*/
|
||||
|
||||
struct ls1x_intc_priv {
|
||||
struct irq_domain *domain;
|
||||
void __iomem *intc_base;
|
||||
};
|
||||
|
||||
|
||||
static void ls1x_chained_handle_irq(struct irq_desc *desc)
|
||||
{
|
||||
struct ls1x_intc_priv *priv = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u32 pending;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
pending = readl(priv->intc_base + LS_REG_INTC_STATUS) &
|
||||
readl(priv->intc_base + LS_REG_INTC_EN);
|
||||
|
||||
if (!pending)
|
||||
spurious_interrupt();
|
||||
|
||||
while (pending) {
|
||||
int bit = __ffs(pending);
|
||||
|
||||
generic_handle_irq(irq_find_mapping(priv->domain, bit));
|
||||
pending &= ~BIT(bit);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void ls_intc_set_bit(struct irq_chip_generic *gc,
|
||||
unsigned int offset,
|
||||
u32 mask, bool set)
|
||||
{
|
||||
if (set)
|
||||
writel(readl(gc->reg_base + offset) | mask,
|
||||
gc->reg_base + offset);
|
||||
else
|
||||
writel(readl(gc->reg_base + offset) & ~mask,
|
||||
gc->reg_base + offset);
|
||||
}
|
||||
|
||||
static int ls_intc_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
|
||||
u32 mask = data->mask;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irqd_set_trigger_type(data, type);
|
||||
return irq_setup_alt_chip(data, type);
|
||||
}
|
||||
|
||||
|
||||
static int __init ls1x_intc_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
struct ls1x_intc_priv *priv;
|
||||
int parent_irq, err = 0;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->intc_base = of_iomap(node, 0);
|
||||
if (!priv->intc_base) {
|
||||
err = -ENODEV;
|
||||
goto out_free_priv;
|
||||
}
|
||||
|
||||
parent_irq = irq_of_parse_and_map(node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("ls1x-irq: unable to get parent irq\n");
|
||||
err = -ENODEV;
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
/* Set up an IRQ domain */
|
||||
priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
|
||||
NULL);
|
||||
if (!priv->domain) {
|
||||
pr_err("ls1x-irq: cannot add IRQ domain\n");
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
err = irq_alloc_domain_generic_chips(priv->domain, 32, 2,
|
||||
node->full_name, handle_level_irq,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0,
|
||||
IRQ_GC_INIT_MASK_CACHE);
|
||||
if (err) {
|
||||
pr_err("ls1x-irq: unable to register IRQ domain\n");
|
||||
goto out_free_domain;
|
||||
}
|
||||
|
||||
/* Mask all irqs */
|
||||
writel(0x0, priv->intc_base + LS_REG_INTC_EN);
|
||||
|
||||
/* Ack all irqs */
|
||||
writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
|
||||
|
||||
/* Set all irqs to high level triggered */
|
||||
writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
|
||||
|
||||
gc = irq_get_domain_generic_chip(priv->domain, 0);
|
||||
|
||||
gc->reg_base = priv->intc_base;
|
||||
|
||||
ct = gc->chip_types;
|
||||
ct[0].type = IRQ_TYPE_LEVEL_MASK;
|
||||
ct[0].regs.mask = LS_REG_INTC_EN;
|
||||
ct[0].regs.ack = LS_REG_INTC_CLR;
|
||||
ct[0].chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct[0].chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct[0].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct[0].chip.irq_set_type = ls_intc_set_type;
|
||||
ct[0].handler = handle_level_irq;
|
||||
|
||||
ct[1].type = IRQ_TYPE_EDGE_BOTH;
|
||||
ct[1].regs.mask = LS_REG_INTC_EN;
|
||||
ct[1].regs.ack = LS_REG_INTC_CLR;
|
||||
ct[1].chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct[1].chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct[1].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct[1].chip.irq_set_type = ls_intc_set_type;
|
||||
ct[1].handler = handle_edge_irq;
|
||||
|
||||
irq_set_chained_handler_and_data(parent_irq,
|
||||
ls1x_chained_handle_irq, priv);
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_domain:
|
||||
irq_domain_remove(priv->domain);
|
||||
out_iounmap:
|
||||
iounmap(priv->intc_base);
|
||||
out_free_priv:
|
||||
kfree(priv);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(ls1x_intc, "loongson,ls1x-intc", ls1x_intc_of_init);
|
||||
|
|
@ -59,62 +59,83 @@ static void __iomem *plic_regs;
|
|||
|
||||
struct plic_handler {
|
||||
bool present;
|
||||
int ctxid;
|
||||
void __iomem *hart_base;
|
||||
/*
|
||||
* Protect mask operations on the registers given that we can't
|
||||
* assume atomic memory operations work on them.
|
||||
*/
|
||||
raw_spinlock_t enable_lock;
|
||||
void __iomem *enable_base;
|
||||
};
|
||||
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
|
||||
|
||||
static inline void __iomem *plic_hart_offset(int ctxid)
|
||||
static inline void plic_toggle(struct plic_handler *handler,
|
||||
int hwirq, int enable)
|
||||
{
|
||||
return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
|
||||
}
|
||||
|
||||
static inline u32 __iomem *plic_enable_base(int ctxid)
|
||||
{
|
||||
return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
|
||||
}
|
||||
|
||||
/*
|
||||
* Protect mask operations on the registers given that we can't assume that
|
||||
* atomic memory operations work on them.
|
||||
*/
|
||||
static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
|
||||
|
||||
static inline void plic_toggle(int ctxid, int hwirq, int enable)
|
||||
{
|
||||
u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
|
||||
u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32);
|
||||
u32 hwirq_mask = 1 << (hwirq % 32);
|
||||
|
||||
raw_spin_lock(&plic_toggle_lock);
|
||||
raw_spin_lock(&handler->enable_lock);
|
||||
if (enable)
|
||||
writel(readl(reg) | hwirq_mask, reg);
|
||||
else
|
||||
writel(readl(reg) & ~hwirq_mask, reg);
|
||||
raw_spin_unlock(&plic_toggle_lock);
|
||||
raw_spin_unlock(&handler->enable_lock);
|
||||
}
|
||||
|
||||
static inline void plic_irq_toggle(struct irq_data *d, int enable)
|
||||
static inline void plic_irq_toggle(const struct cpumask *mask,
|
||||
int hwirq, int enable)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
|
||||
for_each_cpu(cpu, irq_data_get_affinity_mask(d)) {
|
||||
writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
|
||||
for_each_cpu(cpu, mask) {
|
||||
struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
|
||||
|
||||
if (handler->present)
|
||||
plic_toggle(handler->ctxid, d->hwirq, enable);
|
||||
plic_toggle(handler, hwirq, enable);
|
||||
}
|
||||
}
|
||||
|
||||
static void plic_irq_enable(struct irq_data *d)
|
||||
{
|
||||
plic_irq_toggle(d, 1);
|
||||
unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
|
||||
cpu_online_mask);
|
||||
if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
|
||||
return;
|
||||
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
|
||||
}
|
||||
|
||||
static void plic_irq_disable(struct irq_data *d)
|
||||
{
|
||||
plic_irq_toggle(d, 0);
|
||||
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int plic_set_affinity(struct irq_data *d,
|
||||
const struct cpumask *mask_val, bool force)
|
||||
{
|
||||
unsigned int cpu;
|
||||
|
||||
if (force)
|
||||
cpu = cpumask_first(mask_val);
|
||||
else
|
||||
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
||||
|
||||
if (cpu >= nr_cpu_ids)
|
||||
return -EINVAL;
|
||||
|
||||
if (!irqd_irq_disabled(d)) {
|
||||
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
|
||||
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
|
||||
}
|
||||
|
||||
irq_data_update_effective_affinity(d, cpumask_of(cpu));
|
||||
|
||||
return IRQ_SET_MASK_OK_DONE;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct irq_chip plic_chip = {
|
||||
.name = "SiFive PLIC",
|
||||
/*
|
||||
|
|
@ -123,6 +144,9 @@ static struct irq_chip plic_chip = {
|
|||
*/
|
||||
.irq_enable = plic_irq_enable,
|
||||
.irq_disable = plic_irq_disable,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = plic_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
|
||||
|
|
@ -150,7 +174,7 @@ static struct irq_domain *plic_irqdomain;
|
|||
static void plic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
|
||||
void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
|
||||
void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
|
||||
irq_hw_number_t hwirq;
|
||||
|
||||
WARN_ON_ONCE(!handler->present);
|
||||
|
|
@ -186,7 +210,7 @@ static int plic_find_hart_id(struct device_node *node)
|
|||
static int __init plic_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
int error = 0, nr_handlers, nr_mapped = 0, i;
|
||||
int error = 0, nr_contexts, nr_handlers = 0, i;
|
||||
u32 nr_irqs;
|
||||
|
||||
if (plic_regs) {
|
||||
|
|
@ -203,10 +227,10 @@ static int __init plic_init(struct device_node *node,
|
|||
if (WARN_ON(!nr_irqs))
|
||||
goto out_iounmap;
|
||||
|
||||
nr_handlers = of_irq_count(node);
|
||||
if (WARN_ON(!nr_handlers))
|
||||
nr_contexts = of_irq_count(node);
|
||||
if (WARN_ON(!nr_contexts))
|
||||
goto out_iounmap;
|
||||
if (WARN_ON(nr_handlers < num_possible_cpus()))
|
||||
if (WARN_ON(nr_contexts < num_possible_cpus()))
|
||||
goto out_iounmap;
|
||||
|
||||
error = -ENOMEM;
|
||||
|
|
@ -215,7 +239,7 @@ static int __init plic_init(struct device_node *node,
|
|||
if (WARN_ON(!plic_irqdomain))
|
||||
goto out_iounmap;
|
||||
|
||||
for (i = 0; i < nr_handlers; i++) {
|
||||
for (i = 0; i < nr_contexts; i++) {
|
||||
struct of_phandle_args parent;
|
||||
struct plic_handler *handler;
|
||||
irq_hw_number_t hwirq;
|
||||
|
|
@ -237,19 +261,33 @@ static int __init plic_init(struct device_node *node,
|
|||
}
|
||||
|
||||
cpu = riscv_hartid_to_cpuid(hartid);
|
||||
if (cpu < 0) {
|
||||
pr_warn("Invalid cpuid for context %d\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
handler = per_cpu_ptr(&plic_handlers, cpu);
|
||||
if (handler->present) {
|
||||
pr_warn("handler already present for context %d.\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
handler->present = true;
|
||||
handler->ctxid = i;
|
||||
handler->hart_base =
|
||||
plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
|
||||
raw_spin_lock_init(&handler->enable_lock);
|
||||
handler->enable_base =
|
||||
plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
|
||||
|
||||
/* priority must be > threshold to trigger an interrupt */
|
||||
writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
|
||||
writel(0, handler->hart_base + CONTEXT_THRESHOLD);
|
||||
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
|
||||
plic_toggle(i, hwirq, 0);
|
||||
nr_mapped++;
|
||||
plic_toggle(handler, hwirq, 0);
|
||||
nr_handlers++;
|
||||
}
|
||||
|
||||
pr_info("mapped %d interrupts to %d (out of %d) handlers.\n",
|
||||
nr_irqs, nr_mapped, nr_handlers);
|
||||
pr_info("mapped %d interrupts with %d handlers for %d contexts.\n",
|
||||
nr_irqs, nr_handlers, nr_contexts);
|
||||
set_handle_irq(plic_handle_irq);
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -156,6 +156,10 @@ __request_percpu_irq(unsigned int irq, irq_handler_t handler,
|
|||
unsigned long flags, const char *devname,
|
||||
void __percpu *percpu_dev_id);
|
||||
|
||||
extern int __must_check
|
||||
request_nmi(unsigned int irq, irq_handler_t handler, unsigned long flags,
|
||||
const char *name, void *dev);
|
||||
|
||||
static inline int __must_check
|
||||
request_percpu_irq(unsigned int irq, irq_handler_t handler,
|
||||
const char *devname, void __percpu *percpu_dev_id)
|
||||
|
|
@ -164,9 +168,16 @@ request_percpu_irq(unsigned int irq, irq_handler_t handler,
|
|||
devname, percpu_dev_id);
|
||||
}
|
||||
|
||||
extern int __must_check
|
||||
request_percpu_nmi(unsigned int irq, irq_handler_t handler,
|
||||
const char *devname, void __percpu *dev);
|
||||
|
||||
extern const void *free_irq(unsigned int, void *);
|
||||
extern void free_percpu_irq(unsigned int, void __percpu *);
|
||||
|
||||
extern const void *free_nmi(unsigned int irq, void *dev_id);
|
||||
extern void free_percpu_nmi(unsigned int irq, void __percpu *percpu_dev_id);
|
||||
|
||||
struct device;
|
||||
|
||||
extern int __must_check
|
||||
|
|
@ -217,6 +228,13 @@ extern void enable_percpu_irq(unsigned int irq, unsigned int type);
|
|||
extern bool irq_percpu_is_enabled(unsigned int irq);
|
||||
extern void irq_wake_thread(unsigned int irq, void *dev_id);
|
||||
|
||||
extern void disable_nmi_nosync(unsigned int irq);
|
||||
extern void disable_percpu_nmi(unsigned int irq);
|
||||
extern void enable_nmi(unsigned int irq);
|
||||
extern void enable_percpu_nmi(unsigned int irq, unsigned int type);
|
||||
extern int prepare_percpu_nmi(unsigned int irq);
|
||||
extern void teardown_percpu_nmi(unsigned int irq);
|
||||
|
||||
/* The following three functions are for the core kernel use only. */
|
||||
extern void suspend_device_irqs(void);
|
||||
extern void resume_device_irqs(void);
|
||||
|
|
|
|||
|
|
@ -442,6 +442,8 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
|
|||
* @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
|
||||
* @ipi_send_single: send a single IPI to destination cpus
|
||||
* @ipi_send_mask: send an IPI to destination cpus in cpumask
|
||||
* @irq_nmi_setup: function called from core code before enabling an NMI
|
||||
* @irq_nmi_teardown: function called from core code after disabling an NMI
|
||||
* @flags: chip specific flags
|
||||
*/
|
||||
struct irq_chip {
|
||||
|
|
@ -490,6 +492,9 @@ struct irq_chip {
|
|||
void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
|
||||
void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
|
||||
|
||||
int (*irq_nmi_setup)(struct irq_data *data);
|
||||
void (*irq_nmi_teardown)(struct irq_data *data);
|
||||
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
|
|
@ -505,6 +510,7 @@ struct irq_chip {
|
|||
* IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
|
||||
* IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
|
||||
* IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
|
||||
* IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
|
||||
*/
|
||||
enum {
|
||||
IRQCHIP_SET_TYPE_MASKED = (1 << 0),
|
||||
|
|
@ -515,6 +521,7 @@ enum {
|
|||
IRQCHIP_ONESHOT_SAFE = (1 << 5),
|
||||
IRQCHIP_EOI_THREADED = (1 << 6),
|
||||
IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
|
||||
IRQCHIP_SUPPORTS_NMI = (1 << 8),
|
||||
};
|
||||
|
||||
#include <linux/irqdesc.h>
|
||||
|
|
@ -594,6 +601,9 @@ extern void handle_percpu_devid_irq(struct irq_desc *desc);
|
|||
extern void handle_bad_irq(struct irq_desc *desc);
|
||||
extern void handle_nested_irq(unsigned int irq);
|
||||
|
||||
extern void handle_fasteoi_nmi(struct irq_desc *desc);
|
||||
extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
|
||||
|
||||
extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
|
||||
extern int irq_chip_pm_get(struct irq_data *data);
|
||||
extern int irq_chip_pm_put(struct irq_data *data);
|
||||
|
|
|
|||
|
|
@ -173,6 +173,11 @@ static inline int handle_domain_irq(struct irq_domain *domain,
|
|||
{
|
||||
return __handle_domain_irq(domain, hwirq, true, regs);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IRQ_DOMAIN
|
||||
int handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq,
|
||||
struct pt_regs *regs);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Test to see if a driver has successfully requested an irq */
|
||||
|
|
|
|||
|
|
@ -265,6 +265,7 @@ extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
|
|||
enum irq_domain_bus_token bus_token);
|
||||
extern bool irq_domain_check_msi_remap(void);
|
||||
extern void irq_set_default_host(struct irq_domain *host);
|
||||
extern struct irq_domain *irq_get_default_host(void);
|
||||
extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
|
||||
irq_hw_number_t hwirq, int node,
|
||||
const struct irq_affinity_desc *affinity);
|
||||
|
|
|
|||
|
|
@ -729,6 +729,37 @@ void handle_fasteoi_irq(struct irq_desc *desc)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
|
||||
|
||||
/**
|
||||
* handle_fasteoi_nmi - irq handler for NMI interrupt lines
|
||||
* @desc: the interrupt description structure for this irq
|
||||
*
|
||||
* A simple NMI-safe handler, considering the restrictions
|
||||
* from request_nmi.
|
||||
*
|
||||
* Only a single callback will be issued to the chip: an ->eoi()
|
||||
* call when the interrupt has been serviced. This enables support
|
||||
* for modern forms of interrupt handlers, which handle the flow
|
||||
* details in hardware, transparently.
|
||||
*/
|
||||
void handle_fasteoi_nmi(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct irqaction *action = desc->action;
|
||||
unsigned int irq = irq_desc_get_irq(desc);
|
||||
irqreturn_t res;
|
||||
|
||||
trace_irq_handler_entry(irq, action);
|
||||
/*
|
||||
* NMIs cannot be shared, there is only one action.
|
||||
*/
|
||||
res = action->handler(irq, action->dev_id);
|
||||
trace_irq_handler_exit(irq, action, res);
|
||||
|
||||
if (chip->irq_eoi)
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(handle_fasteoi_nmi);
|
||||
|
||||
/**
|
||||
* handle_edge_irq - edge type IRQ handler
|
||||
* @desc: the interrupt description structure for this irq
|
||||
|
|
@ -916,6 +947,29 @@ void handle_percpu_devid_irq(struct irq_desc *desc)
|
|||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
/**
|
||||
* handle_percpu_devid_fasteoi_nmi - Per CPU local NMI handler with per cpu
|
||||
* dev ids
|
||||
* @desc: the interrupt description structure for this irq
|
||||
*
|
||||
* Similar to handle_fasteoi_nmi, but handling the dev_id cookie
|
||||
* as a percpu pointer.
|
||||
*/
|
||||
void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct irqaction *action = desc->action;
|
||||
unsigned int irq = irq_desc_get_irq(desc);
|
||||
irqreturn_t res;
|
||||
|
||||
trace_irq_handler_entry(irq, action);
|
||||
res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
|
||||
trace_irq_handler_exit(irq, action, res);
|
||||
|
||||
if (chip->irq_eoi)
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
static void
|
||||
__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
|
||||
int is_chained, const char *name)
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ static const struct irq_bit_descr irqchip_flags[] = {
|
|||
BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE),
|
||||
BIT_MASK_DESCR(IRQCHIP_EOI_THREADED),
|
||||
BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI),
|
||||
BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI),
|
||||
};
|
||||
|
||||
static void
|
||||
|
|
@ -140,6 +141,7 @@ static const struct irq_bit_descr irqdesc_istates[] = {
|
|||
BIT_MASK_DESCR(IRQS_WAITING),
|
||||
BIT_MASK_DESCR(IRQS_PENDING),
|
||||
BIT_MASK_DESCR(IRQS_SUSPENDED),
|
||||
BIT_MASK_DESCR(IRQS_NMI),
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -203,8 +205,8 @@ static ssize_t irq_debug_write(struct file *file, const char __user *user_buf,
|
|||
chip_bus_lock(desc);
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
|
||||
if (irq_settings_is_level(desc)) {
|
||||
/* Can't do level, sorry */
|
||||
if (irq_settings_is_level(desc) || desc->istate & IRQS_NMI) {
|
||||
/* Can't do level nor NMIs, sorry */
|
||||
err = -EINVAL;
|
||||
} else {
|
||||
desc->istate |= IRQS_PENDING;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ enum {
|
|||
* IRQS_WAITING - irq is waiting
|
||||
* IRQS_PENDING - irq is pending and replayed later
|
||||
* IRQS_SUSPENDED - irq is suspended
|
||||
* IRQS_NMI - irq line is used to deliver NMIs
|
||||
*/
|
||||
enum {
|
||||
IRQS_AUTODETECT = 0x00000001,
|
||||
|
|
@ -60,6 +61,7 @@ enum {
|
|||
IRQS_PENDING = 0x00000200,
|
||||
IRQS_SUSPENDED = 0x00000800,
|
||||
IRQS_TIMINGS = 0x00001000,
|
||||
IRQS_NMI = 0x00002000,
|
||||
};
|
||||
|
||||
#include "debug.h"
|
||||
|
|
|
|||
|
|
@ -670,6 +670,41 @@ int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq,
|
|||
set_irq_regs(old_regs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IRQ_DOMAIN
|
||||
/**
|
||||
* handle_domain_nmi - Invoke the handler for a HW irq belonging to a domain
|
||||
* @domain: The domain where to perform the lookup
|
||||
* @hwirq: The HW irq number to convert to a logical one
|
||||
* @regs: Register file coming from the low-level handling code
|
||||
*
|
||||
* Returns: 0 on success, or -EINVAL if conversion has failed
|
||||
*/
|
||||
int handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *old_regs = set_irq_regs(regs);
|
||||
unsigned int irq;
|
||||
int ret = 0;
|
||||
|
||||
nmi_enter();
|
||||
|
||||
irq = irq_find_mapping(domain, hwirq);
|
||||
|
||||
/*
|
||||
* ack_bad_irq is not NMI-safe, just report
|
||||
* an invalid interrupt.
|
||||
*/
|
||||
if (likely(irq))
|
||||
generic_handle_irq(irq);
|
||||
else
|
||||
ret = -EINVAL;
|
||||
|
||||
nmi_exit();
|
||||
set_irq_regs(old_regs);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Dynamic interrupt handling */
|
||||
|
|
|
|||
|
|
@ -458,6 +458,20 @@ void irq_set_default_host(struct irq_domain *domain)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(irq_set_default_host);
|
||||
|
||||
/**
|
||||
* irq_get_default_host() - Retrieve the "default" irq domain
|
||||
*
|
||||
* Returns: the default domain, if any.
|
||||
*
|
||||
* Modern code should never use this. This should only be used on
|
||||
* systems that cannot implement a firmware->fwnode mapping (which
|
||||
* both DT and ACPI provide).
|
||||
*/
|
||||
struct irq_domain *irq_get_default_host(void)
|
||||
{
|
||||
return irq_default_domain;
|
||||
}
|
||||
|
||||
static void irq_domain_clear_mapping(struct irq_domain *domain,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -341,7 +341,7 @@ irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify)
|
|||
/* The release function is promised process context */
|
||||
might_sleep();
|
||||
|
||||
if (!desc)
|
||||
if (!desc || desc->istate & IRQS_NMI)
|
||||
return -EINVAL;
|
||||
|
||||
/* Complete initialisation of *notify */
|
||||
|
|
@ -553,6 +553,21 @@ bool disable_hardirq(unsigned int irq)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(disable_hardirq);
|
||||
|
||||
/**
|
||||
* disable_nmi_nosync - disable an nmi without waiting
|
||||
* @irq: Interrupt to disable
|
||||
*
|
||||
* Disable the selected interrupt line. Disables and enables are
|
||||
* nested.
|
||||
* The interrupt to disable must have been requested through request_nmi.
|
||||
* Unlike disable_nmi(), this function does not ensure existing
|
||||
* instances of the IRQ handler have completed before returning.
|
||||
*/
|
||||
void disable_nmi_nosync(unsigned int irq)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
}
|
||||
|
||||
void __enable_irq(struct irq_desc *desc)
|
||||
{
|
||||
switch (desc->depth) {
|
||||
|
|
@ -609,6 +624,20 @@ void enable_irq(unsigned int irq)
|
|||
}
|
||||
EXPORT_SYMBOL(enable_irq);
|
||||
|
||||
/**
|
||||
* enable_nmi - enable handling of an nmi
|
||||
* @irq: Interrupt to enable
|
||||
*
|
||||
* The interrupt to enable must have been requested through request_nmi.
|
||||
* Undoes the effect of one call to disable_nmi(). If this
|
||||
* matches the last disable, processing of interrupts on this
|
||||
* IRQ line is re-enabled.
|
||||
*/
|
||||
void enable_nmi(unsigned int irq)
|
||||
{
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
static int set_irq_wake_real(unsigned int irq, unsigned int on)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
|
|
@ -644,6 +673,12 @@ int irq_set_irq_wake(unsigned int irq, unsigned int on)
|
|||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* Don't use NMIs as wake up interrupts please */
|
||||
if (desc->istate & IRQS_NMI) {
|
||||
ret = -EINVAL;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
/* wakeup-capable irqs can be shared between drivers that
|
||||
* don't need to have the same sleep mode behaviors.
|
||||
*/
|
||||
|
|
@ -666,6 +701,8 @@ int irq_set_irq_wake(unsigned int irq, unsigned int on)
|
|||
irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE);
|
||||
}
|
||||
}
|
||||
|
||||
out_unlock:
|
||||
irq_put_desc_busunlock(desc, flags);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1129,6 +1166,39 @@ static void irq_release_resources(struct irq_desc *desc)
|
|||
c->irq_release_resources(d);
|
||||
}
|
||||
|
||||
static bool irq_supports_nmi(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *d = irq_desc_get_irq_data(desc);
|
||||
|
||||
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
||||
/* Only IRQs directly managed by the root irqchip can be set as NMI */
|
||||
if (d->parent_data)
|
||||
return false;
|
||||
#endif
|
||||
/* Don't support NMIs for chips behind a slow bus */
|
||||
if (d->chip->irq_bus_lock || d->chip->irq_bus_sync_unlock)
|
||||
return false;
|
||||
|
||||
return d->chip->flags & IRQCHIP_SUPPORTS_NMI;
|
||||
}
|
||||
|
||||
static int irq_nmi_setup(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *d = irq_desc_get_irq_data(desc);
|
||||
struct irq_chip *c = d->chip;
|
||||
|
||||
return c->irq_nmi_setup ? c->irq_nmi_setup(d) : -EINVAL;
|
||||
}
|
||||
|
||||
static void irq_nmi_teardown(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_data *d = irq_desc_get_irq_data(desc);
|
||||
struct irq_chip *c = d->chip;
|
||||
|
||||
if (c->irq_nmi_teardown)
|
||||
c->irq_nmi_teardown(d);
|
||||
}
|
||||
|
||||
static int
|
||||
setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary)
|
||||
{
|
||||
|
|
@ -1303,9 +1373,17 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
|
|||
* fields must have IRQF_SHARED set and the bits which
|
||||
* set the trigger type must match. Also all must
|
||||
* agree on ONESHOT.
|
||||
* Interrupt lines used for NMIs cannot be shared.
|
||||
*/
|
||||
unsigned int oldtype;
|
||||
|
||||
if (desc->istate & IRQS_NMI) {
|
||||
pr_err("Invalid attempt to share NMI for %s (irq %d) on irqchip %s.\n",
|
||||
new->name, irq, desc->irq_data.chip->name);
|
||||
ret = -EINVAL;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
/*
|
||||
* If nobody did set the configuration before, inherit
|
||||
* the one provided by the requester.
|
||||
|
|
@ -1757,6 +1835,59 @@ const void *free_irq(unsigned int irq, void *dev_id)
|
|||
}
|
||||
EXPORT_SYMBOL(free_irq);
|
||||
|
||||
/* This function must be called with desc->lock held */
|
||||
static const void *__cleanup_nmi(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
const char *devname = NULL;
|
||||
|
||||
desc->istate &= ~IRQS_NMI;
|
||||
|
||||
if (!WARN_ON(desc->action == NULL)) {
|
||||
irq_pm_remove_action(desc, desc->action);
|
||||
devname = desc->action->name;
|
||||
unregister_handler_proc(irq, desc->action);
|
||||
|
||||
kfree(desc->action);
|
||||
desc->action = NULL;
|
||||
}
|
||||
|
||||
irq_settings_clr_disable_unlazy(desc);
|
||||
irq_shutdown(desc);
|
||||
|
||||
irq_release_resources(desc);
|
||||
|
||||
irq_chip_pm_put(&desc->irq_data);
|
||||
module_put(desc->owner);
|
||||
|
||||
return devname;
|
||||
}
|
||||
|
||||
const void *free_nmi(unsigned int irq, void *dev_id)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
unsigned long flags;
|
||||
const void *devname;
|
||||
|
||||
if (!desc || WARN_ON(!(desc->istate & IRQS_NMI)))
|
||||
return NULL;
|
||||
|
||||
if (WARN_ON(irq_settings_is_per_cpu_devid(desc)))
|
||||
return NULL;
|
||||
|
||||
/* NMI still enabled */
|
||||
if (WARN_ON(desc->depth == 0))
|
||||
disable_nmi_nosync(irq);
|
||||
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
|
||||
irq_nmi_teardown(desc);
|
||||
devname = __cleanup_nmi(irq, desc);
|
||||
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
|
||||
return devname;
|
||||
}
|
||||
|
||||
/**
|
||||
* request_threaded_irq - allocate an interrupt line
|
||||
* @irq: Interrupt line to allocate
|
||||
|
|
@ -1926,6 +2057,101 @@ int request_any_context_irq(unsigned int irq, irq_handler_t handler,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(request_any_context_irq);
|
||||
|
||||
/**
|
||||
* request_nmi - allocate an interrupt line for NMI delivery
|
||||
* @irq: Interrupt line to allocate
|
||||
* @handler: Function to be called when the IRQ occurs.
|
||||
* Threaded handler for threaded interrupts.
|
||||
* @irqflags: Interrupt type flags
|
||||
* @name: An ascii name for the claiming device
|
||||
* @dev_id: A cookie passed back to the handler function
|
||||
*
|
||||
* This call allocates interrupt resources and enables the
|
||||
* interrupt line and IRQ handling. It sets up the IRQ line
|
||||
* to be handled as an NMI.
|
||||
*
|
||||
* An interrupt line delivering NMIs cannot be shared and IRQ handling
|
||||
* cannot be threaded.
|
||||
*
|
||||
* Interrupt lines requested for NMI delivering must produce per cpu
|
||||
* interrupts and have auto enabling setting disabled.
|
||||
*
|
||||
* Dev_id must be globally unique. Normally the address of the
|
||||
* device data structure is used as the cookie. Since the handler
|
||||
* receives this value it makes sense to use it.
|
||||
*
|
||||
* If the interrupt line cannot be used to deliver NMIs, function
|
||||
* will fail and return a negative value.
|
||||
*/
|
||||
int request_nmi(unsigned int irq, irq_handler_t handler,
|
||||
unsigned long irqflags, const char *name, void *dev_id)
|
||||
{
|
||||
struct irqaction *action;
|
||||
struct irq_desc *desc;
|
||||
unsigned long flags;
|
||||
int retval;
|
||||
|
||||
if (irq == IRQ_NOTCONNECTED)
|
||||
return -ENOTCONN;
|
||||
|
||||
/* NMI cannot be shared, used for Polling */
|
||||
if (irqflags & (IRQF_SHARED | IRQF_COND_SUSPEND | IRQF_IRQPOLL))
|
||||
return -EINVAL;
|
||||
|
||||
if (!(irqflags & IRQF_PERCPU))
|
||||
return -EINVAL;
|
||||
|
||||
if (!handler)
|
||||
return -EINVAL;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
|
||||
if (!desc || irq_settings_can_autoenable(desc) ||
|
||||
!irq_settings_can_request(desc) ||
|
||||
WARN_ON(irq_settings_is_per_cpu_devid(desc)) ||
|
||||
!irq_supports_nmi(desc))
|
||||
return -EINVAL;
|
||||
|
||||
action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
|
||||
if (!action)
|
||||
return -ENOMEM;
|
||||
|
||||
action->handler = handler;
|
||||
action->flags = irqflags | IRQF_NO_THREAD | IRQF_NOBALANCING;
|
||||
action->name = name;
|
||||
action->dev_id = dev_id;
|
||||
|
||||
retval = irq_chip_pm_get(&desc->irq_data);
|
||||
if (retval < 0)
|
||||
goto err_out;
|
||||
|
||||
retval = __setup_irq(irq, desc, action);
|
||||
if (retval)
|
||||
goto err_irq_setup;
|
||||
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
|
||||
/* Setup NMI state */
|
||||
desc->istate |= IRQS_NMI;
|
||||
retval = irq_nmi_setup(desc);
|
||||
if (retval) {
|
||||
__cleanup_nmi(irq, desc);
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq_setup:
|
||||
irq_chip_pm_put(&desc->irq_data);
|
||||
err_out:
|
||||
kfree(action);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
void enable_percpu_irq(unsigned int irq, unsigned int type)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
|
|
@ -1960,6 +2186,11 @@ void enable_percpu_irq(unsigned int irq, unsigned int type)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(enable_percpu_irq);
|
||||
|
||||
void enable_percpu_nmi(unsigned int irq, unsigned int type)
|
||||
{
|
||||
enable_percpu_irq(irq, type);
|
||||
}
|
||||
|
||||
/**
|
||||
* irq_percpu_is_enabled - Check whether the per cpu irq is enabled
|
||||
* @irq: Linux irq number to check for
|
||||
|
|
@ -1999,6 +2230,11 @@ void disable_percpu_irq(unsigned int irq)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(disable_percpu_irq);
|
||||
|
||||
void disable_percpu_nmi(unsigned int irq)
|
||||
{
|
||||
disable_percpu_irq(irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Internal function to unregister a percpu irqaction.
|
||||
*/
|
||||
|
|
@ -2030,6 +2266,8 @@ static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_
|
|||
/* Found it - now remove it from the list of entries: */
|
||||
desc->action = NULL;
|
||||
|
||||
desc->istate &= ~IRQS_NMI;
|
||||
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
|
||||
unregister_handler_proc(irq, action);
|
||||
|
|
@ -2083,6 +2321,19 @@ void free_percpu_irq(unsigned int irq, void __percpu *dev_id)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(free_percpu_irq);
|
||||
|
||||
void free_percpu_nmi(unsigned int irq, void __percpu *dev_id)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
|
||||
if (!desc || !irq_settings_is_per_cpu_devid(desc))
|
||||
return;
|
||||
|
||||
if (WARN_ON(!(desc->istate & IRQS_NMI)))
|
||||
return;
|
||||
|
||||
kfree(__free_percpu_irq(irq, dev_id));
|
||||
}
|
||||
|
||||
/**
|
||||
* setup_percpu_irq - setup a per-cpu interrupt
|
||||
* @irq: Interrupt line to setup
|
||||
|
|
@ -2172,6 +2423,158 @@ int __request_percpu_irq(unsigned int irq, irq_handler_t handler,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(__request_percpu_irq);
|
||||
|
||||
/**
|
||||
* request_percpu_nmi - allocate a percpu interrupt line for NMI delivery
|
||||
* @irq: Interrupt line to allocate
|
||||
* @handler: Function to be called when the IRQ occurs.
|
||||
* @name: An ascii name for the claiming device
|
||||
* @dev_id: A percpu cookie passed back to the handler function
|
||||
*
|
||||
* This call allocates interrupt resources for a per CPU NMI. Per CPU NMIs
|
||||
* have to be setup on each CPU by calling prepare_percpu_nmi() before
|
||||
* being enabled on the same CPU by using enable_percpu_nmi().
|
||||
*
|
||||
* Dev_id must be globally unique. It is a per-cpu variable, and
|
||||
* the handler gets called with the interrupted CPU's instance of
|
||||
* that variable.
|
||||
*
|
||||
* Interrupt lines requested for NMI delivering should have auto enabling
|
||||
* setting disabled.
|
||||
*
|
||||
* If the interrupt line cannot be used to deliver NMIs, function
|
||||
* will fail returning a negative value.
|
||||
*/
|
||||
int request_percpu_nmi(unsigned int irq, irq_handler_t handler,
|
||||
const char *name, void __percpu *dev_id)
|
||||
{
|
||||
struct irqaction *action;
|
||||
struct irq_desc *desc;
|
||||
unsigned long flags;
|
||||
int retval;
|
||||
|
||||
if (!handler)
|
||||
return -EINVAL;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
|
||||
if (!desc || !irq_settings_can_request(desc) ||
|
||||
!irq_settings_is_per_cpu_devid(desc) ||
|
||||
irq_settings_can_autoenable(desc) ||
|
||||
!irq_supports_nmi(desc))
|
||||
return -EINVAL;
|
||||
|
||||
/* The line cannot already be NMI */
|
||||
if (desc->istate & IRQS_NMI)
|
||||
return -EINVAL;
|
||||
|
||||
action = kzalloc(sizeof(struct irqaction), GFP_KERNEL);
|
||||
if (!action)
|
||||
return -ENOMEM;
|
||||
|
||||
action->handler = handler;
|
||||
action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND | IRQF_NO_THREAD
|
||||
| IRQF_NOBALANCING;
|
||||
action->name = name;
|
||||
action->percpu_dev_id = dev_id;
|
||||
|
||||
retval = irq_chip_pm_get(&desc->irq_data);
|
||||
if (retval < 0)
|
||||
goto err_out;
|
||||
|
||||
retval = __setup_irq(irq, desc, action);
|
||||
if (retval)
|
||||
goto err_irq_setup;
|
||||
|
||||
raw_spin_lock_irqsave(&desc->lock, flags);
|
||||
desc->istate |= IRQS_NMI;
|
||||
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq_setup:
|
||||
irq_chip_pm_put(&desc->irq_data);
|
||||
err_out:
|
||||
kfree(action);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* prepare_percpu_nmi - performs CPU local setup for NMI delivery
|
||||
* @irq: Interrupt line to prepare for NMI delivery
|
||||
*
|
||||
* This call prepares an interrupt line to deliver NMI on the current CPU,
|
||||
* before that interrupt line gets enabled with enable_percpu_nmi().
|
||||
*
|
||||
* As a CPU local operation, this should be called from non-preemptible
|
||||
* context.
|
||||
*
|
||||
* If the interrupt line cannot be used to deliver NMIs, function
|
||||
* will fail returning a negative value.
|
||||
*/
|
||||
int prepare_percpu_nmi(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct irq_desc *desc;
|
||||
int ret = 0;
|
||||
|
||||
WARN_ON(preemptible());
|
||||
|
||||
desc = irq_get_desc_lock(irq, &flags,
|
||||
IRQ_GET_DESC_CHECK_PERCPU);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
if (WARN(!(desc->istate & IRQS_NMI),
|
||||
KERN_ERR "prepare_percpu_nmi called for a non-NMI interrupt: irq %u\n",
|
||||
irq)) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = irq_nmi_setup(desc);
|
||||
if (ret) {
|
||||
pr_err("Failed to setup NMI delivery: irq %u\n", irq);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
irq_put_desc_unlock(desc, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* teardown_percpu_nmi - undoes NMI setup of IRQ line
|
||||
* @irq: Interrupt line from which CPU local NMI configuration should be
|
||||
* removed
|
||||
*
|
||||
* This call undoes the setup done by prepare_percpu_nmi().
|
||||
*
|
||||
* IRQ line should not be enabled for the current CPU.
|
||||
*
|
||||
* As a CPU local operation, this should be called from non-preemptible
|
||||
* context.
|
||||
*/
|
||||
void teardown_percpu_nmi(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct irq_desc *desc;
|
||||
|
||||
WARN_ON(preemptible());
|
||||
|
||||
desc = irq_get_desc_lock(irq, &flags,
|
||||
IRQ_GET_DESC_CHECK_PERCPU);
|
||||
if (!desc)
|
||||
return;
|
||||
|
||||
if (WARN_ON(!(desc->istate & IRQS_NMI)))
|
||||
goto out;
|
||||
|
||||
irq_nmi_teardown(desc);
|
||||
out:
|
||||
irq_put_desc_unlock(desc, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* irq_get_irqchip_state - returns the irqchip state of a interrupt.
|
||||
* @irq: Interrupt line that is forwarded to a VM
|
||||
|
|
|
|||
Loading…
Reference in New Issue