openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

MIPS: Netlogic: Fix frequency calculation register 

Change the PIC frequency calculation to use the register that has the
current configuration. The existing code used the register that is
written to change frequency, which can have an invalid value if the
firmware did not set it up correctly.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8885/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam 2015-01-07 16:58:27 +05:30 committed by Ralf Baechle
parent 72e0605b43
commit a3613be442
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/mips/include/asm/netlogic/xlp-hal/sys.h
View File

@ -177,6 +177,9 @@
#define SYS_9XX_CLK_DEV_DIV 0x18d
#define SYS_9XX_CLK_DEV_CHG 0x18f
#define SYS_9XX_CLK_DEV_SEL_REG 0x1a4
#define SYS_9XX_CLK_DEV_DIV_REG 0x1a6
/* Registers changed on 9XX */
#define SYS_9XX_POWER_ON_RESET_CFG 0x00
#define SYS_9XX_CHIP_RESET 0x01

8
arch/mips/netlogic/xlp/nlm_hal.c
View File

@ -332,7 +332,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
/* Find the clock source PLL device for PIC */
if (cpu_xlp9xx) {
reg_select = nlm_read_sys_reg(clockbase,
SYS_9XX_CLK_DEV_SEL) & 0x3;
SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
switch (reg_select) {
case 0:
ctrl_val0 = nlm_read_sys_reg(clockbase,
@ -361,7 +361,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
}
} else {
reg_select = (nlm_read_sys_reg(sysbase,
SYS_CLK_DEV_SEL) >> 22) & 0x3;
SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
switch (reg_select) {
case 0:
ctrl_val0 = nlm_read_sys_reg(sysbase,
@ -425,10 +425,10 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
/* PIC post divider, which happens after PLL */
if (cpu_xlp9xx)
pic_div = nlm_read_sys_reg(clockbase,
SYS_9XX_CLK_DEV_DIV) & 0x3;
SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
else
pic_div = (nlm_read_sys_reg(sysbase,
SYS_CLK_DEV_DIV) >> 22) & 0x3;
SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
do_div(pll_out_freq_num, 1 << pic_div);
return pll_out_freq_num;