mirror of https://gitee.com/openkylin/linux.git
clk: samsung: exynos7: Constify all clock initializers
All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Krzysztof Kozlowski
Sylwester Nawrocki
parent
880c81b3b6
commit
a3618933c1
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@ -36,7 +36,7 @@
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#define ENABLE_ACLK_TOPC1 0x0804
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#define ENABLE_SCLK_TOPC1 0x0A04
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static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
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static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
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FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus0_pll_div4",
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"ffac_topc_bus0_pll_div2", 1, 2, 0),
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@ -69,7 +69,7 @@ PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
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PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
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"ffac_topc_bus0_pll_div2"};
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static unsigned long topc_clk_regs[] __initdata = {
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static const unsigned long topc_clk_regs[] __initconst = {
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CC_PLL_LOCK,
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BUS0_PLL_LOCK,
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BUS1_DPLL_LOCK,
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@ -89,7 +89,7 @@ static unsigned long topc_clk_regs[] __initdata = {
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DIV_TOPC3,
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};
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static struct samsung_mux_clock topc_mux_clks[] __initdata = {
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static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
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MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
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MUX_SEL_TOPC0, 0, 1),
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MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
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@ -118,7 +118,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
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};
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static struct samsung_div_clock topc_div_clks[] __initdata = {
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static const struct samsung_div_clock topc_div_clks[] __initconst = {
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DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
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DIV_TOPC0, 4, 4),
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@ -139,12 +139,12 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
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DIV_TOPC3, 28, 4),
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};
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static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
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static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
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PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
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{},
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};
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static struct samsung_gate_clock topc_gate_clks[] __initdata = {
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static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
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GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
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ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
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@ -174,7 +174,7 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
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ENABLE_SCLK_TOPC1, 0, 0, 0),
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};
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static struct samsung_pll_clock topc_pll_clks[] __initdata = {
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static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
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PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
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BUS0_PLL_CON0, NULL),
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PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
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@ -187,7 +187,7 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
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AUD_PLL_CON0, pll1460x_24mhz_tbl),
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};
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static struct samsung_cmu_info topc_cmu_info __initdata = {
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static const struct samsung_cmu_info topc_cmu_info __initconst = {
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.pll_clks = topc_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
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.mux_clks = topc_mux_clks,
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@ -256,7 +256,7 @@ PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
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PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
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"mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
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static unsigned long top0_clk_regs[] __initdata = {
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static const unsigned long top0_clk_regs[] __initconst = {
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MUX_SEL_TOP00,
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MUX_SEL_TOP01,
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MUX_SEL_TOP03,
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@ -275,7 +275,7 @@ static unsigned long top0_clk_regs[] __initdata = {
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ENABLE_SCLK_TOP0_PERIC3,
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};
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static struct samsung_mux_clock top0_mux_clks[] __initdata = {
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static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
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MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
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MUX_SEL_TOP00, 0, 1),
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MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
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@ -315,7 +315,7 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
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MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
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};
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static struct samsung_div_clock top0_div_clks[] __initdata = {
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static const struct samsung_div_clock top0_div_clks[] __initconst = {
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DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
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DIV_TOP03, 12, 6),
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DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
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@ -338,7 +338,7 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
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DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
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};
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static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
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GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
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ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
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@ -372,7 +372,7 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
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static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
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FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
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1, 2, 0),
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FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
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@ -381,7 +381,7 @@ static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
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FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
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};
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static struct samsung_cmu_info top0_cmu_info __initdata = {
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static const struct samsung_cmu_info top0_cmu_info __initconst = {
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.mux_clks = top0_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
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.div_clks = top0_div_clks,
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@ -438,7 +438,7 @@ PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
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"mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
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"mout_top1_mfc_pll_half"};
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static unsigned long top1_clk_regs[] __initdata = {
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static const unsigned long top1_clk_regs[] __initconst = {
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MUX_SEL_TOP10,
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MUX_SEL_TOP11,
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MUX_SEL_TOP13,
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@ -455,7 +455,7 @@ static unsigned long top1_clk_regs[] __initdata = {
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ENABLE_SCLK_TOP1_FSYS11,
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};
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static struct samsung_mux_clock top1_mux_clks[] __initdata = {
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static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
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MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
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MUX_SEL_TOP10, 4, 1),
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MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
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@ -494,7 +494,7 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
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MUX_SEL_TOP1_FSYS11, 24, 2),
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};
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static struct samsung_div_clock top1_div_clks[] __initdata = {
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static const struct samsung_div_clock top1_div_clks[] __initconst = {
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DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
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DIV_TOP13, 24, 4),
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DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
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@ -521,7 +521,7 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
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"mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
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};
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static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
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GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
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ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
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GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
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@ -549,7 +549,7 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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24, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
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static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
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FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
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1, 2, 0),
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FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
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@ -558,7 +558,7 @@ static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
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FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
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};
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static struct samsung_cmu_info top1_cmu_info __initdata = {
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static const struct samsung_cmu_info top1_cmu_info __initconst = {
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.mux_clks = top1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
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.div_clks = top1_div_clks,
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@ -592,22 +592,22 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
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*/
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PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
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static unsigned long ccore_clk_regs[] __initdata = {
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static const unsigned long ccore_clk_regs[] __initconst = {
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MUX_SEL_CCORE,
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ENABLE_PCLK_CCORE,
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};
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static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
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static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
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MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
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MUX_SEL_CCORE, 1, 1),
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};
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static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
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static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
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GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
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ENABLE_PCLK_CCORE, 8, 0, 0),
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};
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static struct samsung_cmu_info ccore_cmu_info __initdata = {
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static const struct samsung_cmu_info ccore_cmu_info __initconst = {
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.mux_clks = ccore_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
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.gate_clks = ccore_gate_clks,
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@ -634,20 +634,20 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
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PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
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PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
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static unsigned long peric0_clk_regs[] __initdata = {
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static const unsigned long peric0_clk_regs[] __initconst = {
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MUX_SEL_PERIC0,
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ENABLE_PCLK_PERIC0,
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ENABLE_SCLK_PERIC0,
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};
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static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
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static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
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MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
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MUX_SEL_PERIC0, 0, 1),
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MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
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MUX_SEL_PERIC0, 16, 1),
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};
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static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
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static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
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GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
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ENABLE_PCLK_PERIC0, 8, 0, 0),
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GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
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@ -674,7 +674,7 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
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GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
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};
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static struct samsung_cmu_info peric0_cmu_info __initdata = {
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static const struct samsung_cmu_info peric0_cmu_info __initconst = {
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.mux_clks = peric0_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
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.gate_clks = peric0_gate_clks,
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@ -710,7 +710,7 @@ PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
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PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
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PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
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static unsigned long peric1_clk_regs[] __initdata = {
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static const unsigned long peric1_clk_regs[] __initconst = {
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MUX_SEL_PERIC10,
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MUX_SEL_PERIC11,
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MUX_SEL_PERIC12,
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@ -718,7 +718,7 @@ static unsigned long peric1_clk_regs[] __initdata = {
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ENABLE_SCLK_PERIC10,
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};
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static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
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static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
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MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
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MUX_SEL_PERIC10, 0, 1),
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@ -740,7 +740,7 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
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MUX_SEL_PERIC11, 28, 1),
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};
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static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
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static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
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GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 4, 0, 0),
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GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
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@ -798,7 +798,7 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
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ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_cmu_info peric1_cmu_info __initdata = {
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static const struct samsung_cmu_info peric1_cmu_info __initconst = {
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.mux_clks = peric1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
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.gate_clks = peric1_gate_clks,
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@ -826,7 +826,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
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/* List of parent clocks for Muxes in CMU_PERIS */
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PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
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static unsigned long peris_clk_regs[] __initdata = {
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static const unsigned long peris_clk_regs[] __initconst = {
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MUX_SEL_PERIS,
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ENABLE_PCLK_PERIS,
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ENABLE_PCLK_PERIS_SECURE_CHIPID,
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@ -834,12 +834,12 @@ static unsigned long peris_clk_regs[] __initdata = {
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ENABLE_SCLK_PERIS_SECURE_CHIPID,
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};
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static struct samsung_mux_clock peris_mux_clks[] __initdata = {
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static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
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MUX(0, "mout_aclk_peris_66_user",
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mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
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};
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static struct samsung_gate_clock peris_gate_clks[] __initdata = {
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static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
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GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
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ENABLE_PCLK_PERIS, 6, 0, 0),
|
||||
GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
|
||||
|
|
@ -853,7 +853,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = {
|
|||
GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info peris_cmu_info __initdata = {
|
||||
static const struct samsung_cmu_info peris_cmu_info __initconst = {
|
||||
.mux_clks = peris_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
|
||||
.gate_clks = peris_gate_clks,
|
||||
|
|
@ -894,12 +894,12 @@ PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
|
|||
"phyclk_usbdrd300_udrd30_pipe_pclk" };
|
||||
|
||||
/* fixed rate clocks used in the FSYS0 block */
|
||||
static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
|
||||
static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
|
||||
FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
|
||||
FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
|
||||
};
|
||||
|
||||
static unsigned long fsys0_clk_regs[] __initdata = {
|
||||
static const unsigned long fsys0_clk_regs[] __initconst = {
|
||||
MUX_SEL_FSYS00,
|
||||
MUX_SEL_FSYS01,
|
||||
MUX_SEL_FSYS02,
|
||||
|
|
@ -910,7 +910,7 @@ static unsigned long fsys0_clk_regs[] __initdata = {
|
|||
ENABLE_SCLK_FSYS04,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
|
||||
static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
|
||||
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
|
||||
MUX_SEL_FSYS00, 24, 1),
|
||||
|
||||
|
|
@ -927,7 +927,7 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
|
|||
MUX_SEL_FSYS02, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
|
||||
static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
|
||||
GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS00, 3, 0, 0),
|
||||
GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
|
||||
|
|
@ -961,7 +961,7 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
|
|||
ENABLE_SCLK_FSYS04, 28, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info fsys0_cmu_info __initdata = {
|
||||
static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
|
||||
.fixed_clks = fixed_rate_clks_fsys0,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
|
||||
.mux_clks = fsys0_mux_clks,
|
||||
|
|
@ -1006,7 +1006,7 @@ PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
|
|||
PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
|
||||
|
||||
/* fixed rate clocks used in the FSYS1 block */
|
||||
static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
|
||||
static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
|
||||
FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
|
||||
0, 300000000),
|
||||
FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
|
||||
|
|
@ -1015,7 +1015,7 @@ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
|
|||
0, 300000000),
|
||||
};
|
||||
|
||||
static unsigned long fsys1_clk_regs[] __initdata = {
|
||||
static const unsigned long fsys1_clk_regs[] __initconst = {
|
||||
MUX_SEL_FSYS10,
|
||||
MUX_SEL_FSYS11,
|
||||
MUX_SEL_FSYS12,
|
||||
|
|
@ -1027,7 +1027,7 @@ static unsigned long fsys1_clk_regs[] __initdata = {
|
|||
ENABLE_SCLK_FSYS13,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
|
||||
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
|
||||
MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
|
||||
mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
|
||||
MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
|
||||
|
|
@ -1050,12 +1050,12 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
|
|||
mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock fsys1_div_clks[] __initdata = {
|
||||
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
|
||||
DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
|
||||
DIV_FSYS1, 0, 2),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
|
||||
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
|
||||
GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
|
||||
"mout_sclk_ufsunipro20_user",
|
||||
ENABLE_SCLK_FSYS11, 20, 0, 0),
|
||||
|
|
@ -1090,7 +1090,7 @@ static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
|
|||
ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info fsys1_cmu_info __initdata = {
|
||||
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
|
||||
.fixed_clks = fixed_rate_clks_fsys1,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
|
||||
.mux_clks = fsys1_mux_clks,
|
||||
|
|
@ -1120,22 +1120,22 @@ CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
|
|||
/* List of parent clocks for Muxes in CMU_MSCL */
|
||||
PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
|
||||
|
||||
static unsigned long mscl_clk_regs[] __initdata = {
|
||||
static const unsigned long mscl_clk_regs[] __initconst = {
|
||||
MUX_SEL_MSCL,
|
||||
DIV_MSCL,
|
||||
ENABLE_ACLK_MSCL,
|
||||
ENABLE_PCLK_MSCL,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
|
||||
static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
|
||||
MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
|
||||
mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
|
||||
};
|
||||
static struct samsung_div_clock mscl_div_clks[] __initdata = {
|
||||
static const struct samsung_div_clock mscl_div_clks[] __initconst = {
|
||||
DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
|
||||
DIV_MSCL, 0, 3),
|
||||
};
|
||||
static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
|
||||
static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
|
||||
|
||||
GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
|
||||
ENABLE_ACLK_MSCL, 31, 0, 0),
|
||||
|
|
@ -1205,7 +1205,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
|
|||
ENABLE_PCLK_MSCL, 20, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info mscl_cmu_info __initdata = {
|
||||
static const struct samsung_cmu_info mscl_cmu_info __initconst = {
|
||||
.mux_clks = mscl_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
|
||||
.div_clks = mscl_div_clks,
|
||||
|
|
@ -1239,7 +1239,7 @@ CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
|
|||
PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
|
||||
PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
|
||||
|
||||
static unsigned long aud_clk_regs[] __initdata = {
|
||||
static const unsigned long aud_clk_regs[] __initconst = {
|
||||
MUX_SEL_AUD,
|
||||
DIV_AUD0,
|
||||
DIV_AUD1,
|
||||
|
|
@ -1248,13 +1248,13 @@ static unsigned long aud_clk_regs[] __initdata = {
|
|||
ENABLE_SCLK_AUD,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock aud_mux_clks[] __initdata = {
|
||||
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
|
||||
MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
|
||||
MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
|
||||
MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock aud_div_clks[] __initdata = {
|
||||
static const struct samsung_div_clock aud_div_clks[] __initconst = {
|
||||
DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
|
||||
DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
|
||||
DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
|
||||
|
|
@ -1266,7 +1266,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = {
|
|||
DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock aud_gate_clks[] __initdata = {
|
||||
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
|
||||
GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
|
||||
ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
|
||||
|
|
@ -1294,7 +1294,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
|
|||
GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info aud_cmu_info __initdata = {
|
||||
static const struct samsung_cmu_info aud_cmu_info __initconst = {
|
||||
.mux_clks = aud_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
|
||||
.div_clks = aud_div_clks,
|
||||
|
|
|
|||
Loading…
Reference in New Issue