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drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_set() 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-06-21 11:44:39 +10:00
parent c4c751885e
commit a41ef363f5
6 changed files with 162 additions and 28 deletions
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13
drivers/gpu/drm/nouveau/dispnv50/head507d.c
View File

@ -270,8 +270,13 @@ head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 3)))
return ret;
PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30,
0x0844 + (i * 0x400), asyh->olut.offset >> 8);
PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i),
NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
HEAD_SET_BASE_LUT_HI(i),
NVVAL(NV507D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
return 0;
}
@ -299,9 +304,9 @@ head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
return false;
if (asyh->base.cpp == 1)
asyh->olut.mode = 0;
asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES;
else
asyh->olut.mode = 1;
asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES;
asyh->olut.load = head507d_olut_load;
return true;

14
drivers/gpu/drm/nouveau/dispnv50/head827d.c
View File

@ -24,6 +24,8 @@
#include <nvif/push507c.h>
#include <nvhw/class/cl827d.h>
static int
head827d_curs_clr(struct nv50_head *head)
{
@ -104,9 +106,15 @@ head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 5)))
return ret;
PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30,
0x0844 + (i * 0x400), asyh->olut.offset >> 8);
PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), asyh->olut.handle);
PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
HEAD_SET_BASE_LUT_HI(i),
NVVAL(NV827D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
return 0;
}

18
drivers/gpu/drm/nouveau/dispnv50/head907d.c
View File

@ -235,9 +235,15 @@ head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 5)))
return ret;
PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x80000000 | asyh->olut.mode << 24,
0x044c + (i * 0x300), asyh->olut.offset >> 8);
PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), asyh->olut.handle);
PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |
NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |
NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),
HEAD_SET_OUTPUT_LUT_HI(i),
NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
return 0;
}
@ -264,7 +270,11 @@ head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
if (size != 256 && size != 1024)
return false;
asyh->olut.mode = size == 1024 ? 4 : 7;
if (size == 1024)
asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
else
asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
asyh->olut.load = head907d_olut_load;
return true;
}

20
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
View File

@ -157,11 +157,13 @@ headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 4)))
return ret;
PUSH_NVSQ(push, NVC37D, 0x20a4 + (i * 0x400), asyh->olut.output_mode << 8 |
asyh->olut.range << 4 |
asyh->olut.size,
0x20a8 + (i * 0x400), asyh->olut.offset >> 8,
0x20ac + (i * 0x400), asyh->olut.handle);
PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i),
NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) |
NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) |
NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode),
HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8,
HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle);
return 0;
}
@ -171,10 +173,10 @@ headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
if (size != 256 && size != 1024)
return false;
asyh->olut.mode = 2;
asyh->olut.size = size == 1024 ? 2 : 0;
asyh->olut.range = 0;
asyh->olut.output_mode = 1;
asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 :
NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257;
asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY;
asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE;
asyh->olut.load = head907d_olut_load;
return true;
}

19
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
View File

@ -99,12 +99,15 @@ headc57d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
if ((ret = PUSH_WAIT(push, 5)))
return ret;
PUSH_NVSQ(push, NVC57D, 0x2280 + (i * 0x400), asyh->olut.size << 8 |
asyh->olut.mode << 2 |
asyh->olut.output_mode,
0x2284 + (i * 0x400), 0xffffffff,
0x2288 + (i * 0x400), asyh->olut.handle,
0x228c + (i * 0x400), asyh->olut.offset >> 8);
PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i),
NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) |
NVDEF(NVC57D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |
NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |
NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size),
HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff,
HEAD_SET_CONTEXT_DMA_OLUT(i), asyh->olut.handle,
HEAD_SET_OFFSET_OLUT(i), asyh->olut.offset >> 8);
return 0;
}
@ -167,9 +170,9 @@ headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
if (size != 0 && size != 256 && size != 1024)
return false;
asyh->olut.mode = 2; /* DIRECT10 */
asyh->olut.mode = NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10;
asyh->olut.size = 4 /* VSS header. */ + 1024 + 1 /* Entries. */;
asyh->olut.output_mode = 1; /* INTERPOLATE_ENABLE. */
asyh->olut.output_mode = NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE;
if (size == 256)
asyh->olut.load = headc57d_olut_load_8;
else

106
drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h Normal file
View File

@ -0,0 +1,106 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl827d_h_
#define _cl827d_h_
// class methods
#define NV827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400)
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000)
#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001)
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE 30:30
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000)
#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001)
#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2
#define NV827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400)
#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0
#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0
#define NV827D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_OFFSET_ORIGIN 31:0
#define NV827D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400)
#define NV827D_HEAD_SET_SIZE_WIDTH 14:0
#define NV827D_HEAD_SET_SIZE_HEIGHT 30:16
#define NV827D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV827D_HEAD_SET_STORAGE_PITCH 17:8
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV827D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400)
#define NV827D_HEAD_SET_PARAMS_FORMAT 15:8
#define NV827D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV827D_HEAD_SET_PARAMS_GAMMA 2:2
#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV827D_HEAD_SET_PARAMS_RESERVED0 22:16
#define NV827D_HEAD_SET_PARAMS_RESERVED1 24:24
#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV827D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8
#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003)
#define NV827D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400)
#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0
#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400)
#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004)
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0
#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16
#endif // _cl827d_h