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ARM: tegra: Device tree changes for v4.19-rc1 

This set of changes adds support for the memory client resets on Tegra20
 and Tegra30, fixes a couple of issues on Cardhu and Tegra30 Apalis as
 well as adds a unit-address to the memory node to avoid warnings from
 DTC. To round things of, the NAND flash controller is enabled on the
 Tegra20 Colibri.
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Merge tag 'tegra-for-4.19-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

ARM: tegra: Device tree changes for v4.19-rc1

This set of changes adds support for the memory client resets on Tegra20
and Tegra30, fixes a couple of issues on Cardhu and Tegra30 Apalis as
well as adds a unit-address to the memory node to avoid warnings from
DTC. To round things of, the NAND flash controller is enabled on the
Tegra20 Colibri.

* tag 'tegra-for-4.19-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: dts: tegra: enable NAND flash on Colibri T20
  ARM: dts: tegra: add Tegra20 NAND flash controller node
  ARM: tegra: Work safely with 256 MB Colibri-T20 modules
  ARM: tegra: Fix unit_address_vs_reg and avoid_unnecessary_addr_size DTC warnings
  ARM: tegra: Fix unit_address_vs_reg DTC warnings for /memory
  ARM: tegra: Remove usage of deprecated skeleton.dtsi
  ARM: tegra: Fix can2 on Tegra30 Apalis
  ARM: tegra: Fix Tegra30 Cardhu PCA954x reset
  ARM: dts: tegra30: Add Memory Client reset to VDE
  ARM: dts: tegra20: Add Memory Client reset to VDE

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-14 14:20:50 -07:00
parent 0775f498a7 5def854e37
commit a4c43ba496
25 changed files with 100 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/Makefile
View File

@ -1040,7 +1040,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-colibri-iris.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \

2
arch/arm/boot/dts/tegra114-dalmore.dts
View File

@ -23,7 +23,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x80000000 0x40000000>;
};

2
arch/arm/boot/dts/tegra114-roth.dts
View File

@ -28,7 +28,7 @@ trusted-foundations {
};
};
memory {
memory@80000000 {
/* memory >= 0x79600000 is reserved for firmware usage */
reg = <0x80000000 0x79600000>;
};

2
arch/arm/boot/dts/tegra114-tn7.dts
View File

@ -28,7 +28,7 @@ trusted-foundations {
};
};
memory {
memory@80000000 {
/* memory >= 0x37e00000 is reserved for firmware usage */
reg = <0x80000000 0x37e00000>;
};

9
arch/arm/boot/dts/tegra114.dtsi
View File

@ -5,11 +5,16 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
interrupt-parent = <&lic>;
#address-cells = <1>;
#size-cells = <1>;
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x0>;
};
host1x@50000000 {
compatible = "nvidia,tegra114-host1x", "simple-bus";

2
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
View File

@ -15,7 +15,7 @@ / {
compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
"nvidia,tegra124";
memory {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};

2
arch/arm/boot/dts/tegra124-apalis.dtsi
View File

@ -50,7 +50,7 @@ / {
model = "Toradex Apalis TK1";
compatible = "toradex,apalis-tk1", "nvidia,tegra124";
memory {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};

2
arch/arm/boot/dts/tegra124-jetson-tk1.dts
View File

@ -24,7 +24,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};

2
arch/arm/boot/dts/tegra124-nyan.dtsi
View File

@ -13,7 +13,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};

2
arch/arm/boot/dts/tegra124-venice2.dts
View File

@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};

7
arch/arm/boot/dts/tegra124.dtsi
View File

@ -7,14 +7,17 @@
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra124";
interrupt-parent = <&lic>;
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x0>;
};
pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";

4
arch/arm/boot/dts/tegra20-iris-512.dts → arch/arm/boot/dts/tegra20-colibri-iris.dts
View File

@ -1,10 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra20-colibri-512.dtsi"
#include "tegra20-colibri.dtsi"
/ {
model = "Toradex Colibri T20 512MB on Iris";
model = "Toradex Colibri T20 256/512 MB on Iris";
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
aliases {

27
arch/arm/boot/dts/tegra20-colibri-512.dtsi → arch/arm/boot/dts/tegra20-colibri.dtsi
View File

@ -2,7 +2,7 @@
#include "tegra20.dtsi"
/ {
model = "Toradex Colibri T20 512MB";
model = "Toradex Colibri T20 256/512 MB";
compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
aliases {
@ -10,8 +10,13 @@ aliases {
rtc1 = "/rtc@7000e000";
};
memory {
reg = <0x00000000 0x20000000>;
memory@0 {
/*
* Set memory to 256 MB to be safe as this could be used on
* 256 or 512 MB module. It is expected from bootloader
* to fix this up for 512 MB version.
*/
reg = <0x00000000 0x10000000>;
};
host1x@50000000 {
@ -213,6 +218,22 @@ ac97: ac97@70002000 {
GPIO_ACTIVE_HIGH>;
};
nand-controller@70008000 {
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-on-flash-bbt;
nand-ecc-algo = "bch";
nand-is-boot-medium;
nand-ecc-maximize;
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
};
};
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)

2
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x40000000>;
};

2
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -19,7 +19,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x20000000>;
};

2
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x40000000>;
};

2
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -15,7 +15,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x20000000>;
};

2
arch/arm/boot/dts/tegra20-trimslice.dts
View File

@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x40000000>;
};

2
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -18,7 +18,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
reg = <0x00000000 0x40000000>;
};

31
arch/arm/boot/dts/tegra20.dtsi
View File

@ -1,14 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra20-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
interrupt-parent = <&lic>;
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0 0>;
};
iram@40000000 {
compatible = "mmio-sram";
@ -282,7 +288,8 @@ vde@6001a000 {
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
interrupt-names = "sync-token", "bsev", "sxe";
clocks = <&tegra_car TEGRA20_CLK_VDE>;
resets = <&tegra_car 61>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
};
apbmisc@70000800 {
@ -425,6 +432,21 @@ gmi@70009000 {
status = "disabled";
};
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
clock-names = "nand";
resets = <&tegra_car 13>;
reset-names = "nand";
assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
assigned-clock-rates = <150000000>;
status = "disabled";
};
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
@ -593,11 +615,12 @@ pmc@7000e400 {
clock-names = "pclk", "clk32k_in";
};
memory-controller@7000f000 {
mc: memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
iommu@7000f024 {

9
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -10,6 +10,10 @@ / {
model = "Toradex Apalis T30";
compatible = "toradex,apalis_t30", "nvidia,tegra30";
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
pcie@3000 {
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
@ -118,6 +122,7 @@ gmi_a16_pj7 {
nvidia,function = "spi4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* CAN_INT2 */
spi2_cs2_n_pw3 {
@ -585,8 +590,6 @@ ldo8_reg: ldo8 {
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio>;
@ -595,7 +598,7 @@ stmpe811@41 {
blocks = <0x5>;
irq-trigger = <0x1>;
stmpe_touchscreen@0 {
stmpe_touchscreen {
compatible = "st,stmpe-ts";
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;

5
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -17,7 +17,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x80000000 0x7ff00000>;
};
@ -1790,9 +1790,6 @@ pmic: tps65911@2d {
vccio-supply = <&vdd_5v_in_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;

3
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -40,7 +40,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@ -206,6 +206,7 @@ i2cmux@70 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
};
};

4
arch/arm/boot/dts/tegra30-colibri.dtsi
View File

@ -10,7 +10,7 @@ / {
model = "Toradex Colibri T30";
compatible = "toradex,colibri_t30", "nvidia,tegra30";
memory {
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
@ -351,8 +351,6 @@ ldo8_reg: ldo8 {
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio>;

13
arch/arm/boot/dts/tegra30.dtsi
View File

@ -5,11 +5,16 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
#address-cells = <1>;
#size-cells = <1>;
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x0>;
};
pcie@3000 {
compatible = "nvidia,tegra30-pcie";
@ -404,7 +409,8 @@ vde@6001a000 {
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
interrupt-names = "sync-token", "bsev", "sxe";
clocks = <&tegra_car TEGRA30_CLK_VDE>;
resets = <&tegra_car 61>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
};
apbmisc@70000800 {
@ -712,6 +718,7 @@ mc: memory-controller@7000f000 {
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
};
fuse@7000f800 {