mirror of https://gitee.com/openkylin/linux.git
Renesas ARM Based SoC Updates for v4.18
* SoC
- Change platform dependency to ARCH_RENESAS
Geert Uytterhoeven says "The Renesas Fine Display Processor driver is
used on Renesas R-Car SoCs only. Since commit 9b5ba0df4e ("ARM:
shmobile: Introduce ARCH_RENESAS") is ARCH_RENESAS a more appropriate
platform dependency than the legacy ARCH_SHMOBILE, hence use the
former.
This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
future."
- Add the to Kconfig RZ/N1D (r9a06g032) SoC
In preparation for upstream support of this SoC
- Identify R-Car E3 (r8a77990) SoC
- Identify and add minimal support for RZ/G1C (r8a77470) SoC
* R-Car SYSC
- Add support for R-Car E3 (r8a77990) SoC
Shimoda-san says this adds:
+ "Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC,
A2VC1 and 3DG-{A,B} power domain areas..."
+ "workaround for 3DG-{A,B} of R-Car E3 ES1.0 because
the SoC has a restriction about the order."
- Remove unused inclusion of <linux/sys_soc.h>,
- Make r8a77995_areas[] const.
* R-Car Reset
- Add support for R-Car E3 (r8a77990) SoC
This driver is needed for the clock driver to work
* Debug-LL
- Add support for RZ/G1C (r8a77470) SoC
RZ/G1C uses SCIF1 for the debug console
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Merge tag 'renesas-soc-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Renesas ARM Based SoC Updates for v4.18
* SoC
- Change platform dependency to ARCH_RENESAS
This will allow to drop ARCH_SHMOBILE on ARM and ARM64 in the near
future.
- Add the to Kconfig RZ/N1D (r9a06g032) SoC
- Identify R-Car E3 (r8a77990) SoC
- Identify and add minimal support for RZ/G1C (r8a77470) SoC
* R-Car SYSC
- Add support for R-Car E3 (r8a77990) SoC
- Remove unused inclusion of <linux/sys_soc.h>,
- Make r8a77995_areas[] const.
* R-Car Reset
- Add support for R-Car E3 (r8a77990) SoC
* Debug-LL
- Add support for RZ/G1C (r8a77470) SoC
* tag 'renesas-soc-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}
soc: renesas: rcar-sysc: Add support for R-Car E3 power areas
arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
arm: shmobile: Change platform dependency to ARCH_RENESAS
soc: renesas: r8a77995-sysc: Cleanups
soc: renesas: rcar-rst: Add support for R-Car E3
soc: renesas: Add r8a77990 SYSC PM Domain Binding Definitions
soc: renesas: identify R-Car E3
ARM: debug-ll: Add support for r8a77470
ARM: shmobile: Add the RZ/N1 arch to the shmobile Kconfig
ARM: shmobile: r8a77470: basic SoC support
soc: renesas: rcar-sysc: Add r8a77470 support
soc: renesas: rcar-rst: Add support for RZ/G1C
soc: renesas: Identify RZ/G1C
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a51dcd297d
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@ -21,6 +21,8 @@ SoCs:
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compatible = "renesas,r8a7744"
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- RZ/G1E (R8A77450)
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compatible = "renesas,r8a7745"
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- RZ/G1C (R8A77470)
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compatible = "renesas,r8a77470"
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- R-Car M1A (R8A77781)
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compatible = "renesas,r8a7778"
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- R-Car H1 (R8A77790)
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@ -9,6 +9,7 @@ Required properties:
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- compatible: Must contain exactly one of the following:
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- "renesas,r8a7743-sysc" (RZ/G1M)
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- "renesas,r8a7745-sysc" (RZ/G1E)
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- "renesas,r8a77470-sysc" (RZ/G1C)
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- "renesas,r8a7779-sysc" (R-Car H1)
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- "renesas,r8a7790-sysc" (R-Car H2)
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- "renesas,r8a7791-sysc" (R-Car M2-W)
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@ -20,6 +21,7 @@ Required properties:
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- "renesas,r8a77965-sysc" (R-Car M3-N)
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- "renesas,r8a77970-sysc" (R-Car V3M)
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- "renesas,r8a77980-sysc" (R-Car V3H)
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- "renesas,r8a77990-sysc" (R-Car E3)
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- "renesas,r8a77995-sysc" (R-Car D3)
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- reg: Address start and address range for the device.
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- #power-domain-cells: Must be 1.
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@ -17,6 +17,7 @@ Required properties:
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Examples with soctypes are:
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- "renesas,r8a7743-rst" (RZ/G1M)
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- "renesas,r8a7745-rst" (RZ/G1E)
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- "renesas,r8a77470-rst" (RZ/G1C)
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- "renesas,r8a7778-reset-wdt" (R-Car M1A)
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- "renesas,r8a7779-reset-wdt" (R-Car H1)
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- "renesas,r8a7790-rst" (R-Car H2)
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@ -29,6 +30,7 @@ Required properties:
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- "renesas,r8a77965-rst" (R-Car M3-N)
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- "renesas,r8a77970-rst" (R-Car V3M)
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- "renesas,r8a77980-rst" (R-Car V3H)
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- "renesas,r8a77990-rst" (R-Car E3)
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- "renesas,r8a77995-rst" (R-Car D3)
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- reg: Address start and address range for the device.
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@ -1467,7 +1467,7 @@ config ARM_PSCI
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config ARCH_NR_GPIO
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int
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default 2048 if ARCH_SOCFPGA
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default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
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default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
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ARCH_ZYNQ
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default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
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SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
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@ -942,6 +942,13 @@ choice
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via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790),
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M2-W (R8A7791), V2H (R8A7792), or M2-N (R8A7793).
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config DEBUG_RCAR_GEN2_SCIF1
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bool "Kernel low-level debugging messages via SCIF1 on R8A77470"
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depends on ARCH_R8A77470
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help
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Say Y here if you want kernel low-level debugging support
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via SCIF1 on Renesas RZ/G1C (R8A77470).
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config DEBUG_RCAR_GEN2_SCIF2
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bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
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depends on ARCH_R8A7794
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@ -1495,6 +1502,7 @@ config DEBUG_LL_INCLUDE
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
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default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
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@ -1617,6 +1625,7 @@ config DEBUG_UART_PHYS
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default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
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default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
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default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
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default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
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default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
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default 0xe8008000 if DEBUG_R7S72100_SCIF2
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default 0xf0000be0 if ARCH_EBSA110
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@ -1651,8 +1660,8 @@ config DEBUG_UART_PHYS
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DEBUG_NETX_UART || \
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DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
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DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
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DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
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DEBUG_RCAR_GEN2_SCIF4 || \
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DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
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DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
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DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
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DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
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DEBUG_S3C64XX_UART || \
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@ -212,7 +212,7 @@ machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
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machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
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machine-$(CONFIG_ARCH_S5PV210) += s5pv210
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machine-$(CONFIG_ARCH_SA1100) += sa1100
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machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
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machine-$(CONFIG_ARCH_RENESAS) += shmobile
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machine-$(CONFIG_ARCH_SIRF) += prima2
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machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
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machine-$(CONFIG_ARCH_STI) += sti
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@ -75,6 +75,10 @@ config ARCH_R8A7745
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bool "RZ/G1E (R8A77450)"
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select ARCH_RCAR_GEN2
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config ARCH_R8A77470
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bool "RZ/G1C (R8A77470)"
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select ARCH_RCAR_GEN2
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config ARCH_R8A7778
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bool "R-Car M1A (R8A77781)"
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select ARCH_RCAR_GEN1
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@ -110,6 +114,15 @@ config ARCH_R8A7794
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bool "R-Car E2 (R8A77940)"
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select ARCH_RCAR_GEN2
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config ARCH_R9A06G032
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bool "RZ/N1D (R9A06G032)"
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select ARCH_RZN1
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config ARCH_RZN1
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bool "RZ/N1 (R9A06G0xx) Family"
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select ARM_AMBA
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select CPU_V7
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config ARCH_SH73A0
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bool "SH-Mobile AG5 (R8A73A00)"
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select ARCH_RMOBILE
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@ -74,6 +74,7 @@ void __init rcar_gen2_timer_init(void)
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secure_cntvoff_init();
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if (of_machine_is_compatible("renesas,r8a7745") ||
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of_machine_is_compatible("renesas,r8a77470") ||
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of_machine_is_compatible("renesas,r8a7792") ||
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of_machine_is_compatible("renesas,r8a7794")) {
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freq = 260000000 / 8; /* ZS / 8 */
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@ -206,6 +207,7 @@ MACHINE_END
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static const char * const rz_g1_boards_compat_dt[] __initconst = {
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"renesas,r8a7743",
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"renesas,r8a7745",
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"renesas,r8a77470",
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NULL,
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};
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@ -4,9 +4,11 @@ config SOC_RENESAS
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select SOC_BUS
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select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
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ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \
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ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77995
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ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \
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ARCH_R8A77995
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select SYSC_R8A7743 if ARCH_R8A7743
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select SYSC_R8A7745 if ARCH_R8A7745
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select SYSC_R8A77470 if ARCH_R8A77470
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select SYSC_R8A7779 if ARCH_R8A7779
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select SYSC_R8A7790 if ARCH_R8A7790
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select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
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@ -17,6 +19,7 @@ config SOC_RENESAS
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select SYSC_R8A77965 if ARCH_R8A77965
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select SYSC_R8A77970 if ARCH_R8A77970
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select SYSC_R8A77980 if ARCH_R8A77980
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select SYSC_R8A77990 if ARCH_R8A77990
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select SYSC_R8A77995 if ARCH_R8A77995
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if SOC_RENESAS
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@ -30,6 +33,10 @@ config SYSC_R8A7745
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bool "RZ/G1E System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77470
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bool "RZ/G1C System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A7779
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bool "R-Car H1 System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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@ -70,6 +77,10 @@ config SYSC_R8A77980
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bool "R-Car V3H System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77990
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bool "R-Car E3 System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77995
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bool "R-Car D3 System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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@ -5,6 +5,7 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
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# SoC
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obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
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obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
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obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
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obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
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obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
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obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o
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@ -15,6 +16,7 @@ obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
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obj-$(CONFIG_SYSC_R8A77965) += r8a77965-sysc.o
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obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
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obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o
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obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
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obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
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# Family
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|
|
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G1C System Controller
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a77470-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a77470_areas[] __initconst = {
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{ "always-on", 0, 0, R8A77470_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca7-scu", 0x100, 0, R8A77470_PD_CA7_SCU, R8A77470_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca7-cpu0", 0x1c0, 0, R8A77470_PD_CA7_CPU0, R8A77470_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu1", 0x1c0, 1, R8A77470_PD_CA7_CPU1, R8A77470_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "sgx", 0xc0, 0, R8A77470_PD_SGX, R8A77470_PD_ALWAYS_ON },
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};
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const struct rcar_sysc_info r8a77470_sysc_info __initconst = {
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.areas = r8a77470_areas,
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.num_areas = ARRAY_SIZE(r8a77470_areas),
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};
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|
|
@ -0,0 +1,68 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
|
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* Renesas R-Car E3 System Controller
|
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*
|
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* Copyright (C) 2018 Renesas Electronics Corp.
|
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*/
|
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|
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#include <linux/bug.h>
|
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#include <linux/kernel.h>
|
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#include <linux/sys_soc.h>
|
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|
||||
#include <dt-bindings/power/r8a77990-sysc.h>
|
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|
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#include "rcar-sysc.h"
|
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|
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static struct rcar_sysc_area r8a77990_areas[] __initdata = {
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{ "always-on", 0, 0, R8A77990_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
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{ "ca53-scu", 0x140, 0, R8A77990_PD_CA53_SCU, R8A77990_PD_ALWAYS_ON,
|
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PD_SCU },
|
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{ "ca53-cpu0", 0x200, 0, R8A77990_PD_CA53_CPU0, R8A77990_PD_CA53_SCU,
|
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PD_CPU_NOCR },
|
||||
{ "ca53-cpu1", 0x200, 1, R8A77990_PD_CA53_CPU1, R8A77990_PD_CA53_SCU,
|
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PD_CPU_NOCR },
|
||||
{ "cr7", 0x240, 0, R8A77990_PD_CR7, R8A77990_PD_ALWAYS_ON },
|
||||
{ "a3vc", 0x380, 0, R8A77990_PD_A3VC, R8A77990_PD_ALWAYS_ON },
|
||||
{ "a2vc1", 0x3c0, 1, R8A77990_PD_A2VC1, R8A77990_PD_A3VC },
|
||||
{ "3dg-a", 0x100, 0, R8A77990_PD_3DG_A, R8A77990_PD_ALWAYS_ON },
|
||||
{ "3dg-b", 0x100, 1, R8A77990_PD_3DG_B, R8A77990_PD_3DG_A },
|
||||
};
|
||||
|
||||
static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
|
||||
unsigned int num_areas, u8 id,
|
||||
int new_parent)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num_areas; i++)
|
||||
if (areas[i].isr_bit == id) {
|
||||
areas[i].parent = new_parent;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fixups for R-Car E3 ES1.0 revision */
|
||||
static const struct soc_device_attribute r8a77990[] __initconst = {
|
||||
{ .soc_id = "r8a77990", .revision = "ES1.0" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int __init r8a77990_sysc_init(void)
|
||||
{
|
||||
if (soc_device_match(r8a77990)) {
|
||||
rcar_sysc_fix_parent(r8a77990_areas,
|
||||
ARRAY_SIZE(r8a77990_areas),
|
||||
R8A77990_PD_3DG_A, R8A77990_PD_3DG_B);
|
||||
rcar_sysc_fix_parent(r8a77990_areas,
|
||||
ARRAY_SIZE(r8a77990_areas),
|
||||
R8A77990_PD_3DG_B, R8A77990_PD_ALWAYS_ON);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rcar_sysc_info r8a77990_sysc_info __initconst = {
|
||||
.init = r8a77990_sysc_init,
|
||||
.areas = r8a77990_areas,
|
||||
.num_areas = ARRAY_SIZE(r8a77990_areas),
|
||||
};
|
||||
|
|
@ -10,13 +10,12 @@
|
|||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include <dt-bindings/power/r8a77995-sysc.h>
|
||||
|
||||
#include "rcar-sysc.h"
|
||||
|
||||
static struct rcar_sysc_area r8a77995_areas[] __initdata = {
|
||||
static const struct rcar_sysc_area r8a77995_areas[] __initconst = {
|
||||
{ "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
|
||||
{ "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
|
||||
PD_SCU },
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
|
|||
/* RZ/G is handled like R-Car Gen2 */
|
||||
{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
|
||||
{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
|
||||
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
|
||||
/* R-Car Gen1 */
|
||||
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
|
||||
{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
|
||||
|
|
@ -59,6 +60,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
|
|||
{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
|
||||
{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -261,6 +261,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
|
|||
#ifdef CONFIG_SYSC_R8A7745
|
||||
{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A77470
|
||||
{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A7779
|
||||
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
|
||||
#endif
|
||||
|
|
@ -293,6 +296,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
|
|||
#ifdef CONFIG_SYSC_R8A77980
|
||||
{ .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A77990
|
||||
{ .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
|
||||
#endif
|
||||
#ifdef CONFIG_SYSC_R8A77995
|
||||
{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ struct rcar_sysc_info {
|
|||
|
||||
extern const struct rcar_sysc_info r8a7743_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7745_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a77470_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7779_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7790_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a7791_sysc_info;
|
||||
|
|
@ -61,6 +62,7 @@ extern const struct rcar_sysc_info r8a7796_sysc_info;
|
|||
extern const struct rcar_sysc_info r8a77965_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a77970_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a77980_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a77990_sysc_info;
|
||||
extern const struct rcar_sysc_info r8a77995_sysc_info;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -100,6 +100,11 @@ static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = {
|
|||
.id = 0x4c,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rz_g1c __initconst __maybe_unused = {
|
||||
.family = &fam_rzg,
|
||||
.id = 0x53,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen1,
|
||||
};
|
||||
|
|
@ -159,6 +164,11 @@ static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
|
|||
.id = 0x56,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_e3 __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen3,
|
||||
.id = 0x57,
|
||||
};
|
||||
|
||||
static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
|
||||
.family = &fam_rcar_gen3,
|
||||
.id = 0x58,
|
||||
|
|
@ -192,6 +202,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
|
|||
#ifdef CONFIG_ARCH_R8A7745
|
||||
{ .compatible = "renesas,r8a7745", .data = &soc_rz_g1e },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A77470
|
||||
{ .compatible = "renesas,r8a77470", .data = &soc_rz_g1c },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7778
|
||||
{ .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
|
||||
#endif
|
||||
|
|
@ -228,6 +241,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
|
|||
#ifdef CONFIG_ARCH_R8A77980
|
||||
{ .compatible = "renesas,r8a77980", .data = &soc_rcar_v3h },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A77990
|
||||
{ .compatible = "renesas,r8a77990", .data = &soc_rcar_e3 },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A77995
|
||||
{ .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 },
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77470_PD_CA7_CPU0 5
|
||||
#define R8A77470_PD_CA7_CPU1 6
|
||||
#define R8A77470_PD_SGX 20
|
||||
#define R8A77470_PD_CA7_SCU 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77470_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77990_PD_CA53_CPU0 5
|
||||
#define R8A77990_PD_CA53_CPU1 6
|
||||
#define R8A77990_PD_CR7 13
|
||||
#define R8A77990_PD_A3VC 14
|
||||
#define R8A77990_PD_3DG_A 17
|
||||
#define R8A77990_PD_3DG_B 18
|
||||
#define R8A77990_PD_CA53_SCU 21
|
||||
#define R8A77990_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77990_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
|
||||
Loading…
Reference in New Issue