mirror of https://gitee.com/openkylin/linux.git
ARM: imx31: Remove remaining i.MX31 board code
i.MX31 is a devicetree only platform. Remove remaining i.MX31 board code. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam
Shawn Guo
parent
fc673fbf8c
commit
a542fc1816
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@ -1,207 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/smsc911x.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/fixed.h>
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#include "3ds_debugboard.h"
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#include "hardware.h"
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/* LAN9217 ethernet base address */
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#define LAN9217_BASE_ADDR(n) (n + 0x0)
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/* External UART */
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#define UARTA_BASE_ADDR(n) (n + 0x8000)
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#define UARTB_BASE_ADDR(n) (n + 0x10000)
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#define BOARD_IO_ADDR(n) (n + 0x20000)
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/* LED switchs */
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#define LED_SWITCH_REG 0x00
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/* buttons */
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#define SWITCH_BUTTONS_REG 0x08
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/* status, interrupt */
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#define INTR_STATUS_REG 0x10
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#define INTR_MASK_REG 0x38
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#define INTR_RESET_REG 0x20
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/* magic word for debug CPLD */
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#define MAGIC_NUMBER1_REG 0x40
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#define MAGIC_NUMBER2_REG 0x48
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/* CPLD code version */
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#define CPLD_CODE_VER_REG 0x50
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/* magic word for debug CPLD */
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#define MAGIC_NUMBER3_REG 0x58
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/* module reset register*/
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#define MODULE_RESET_REG 0x60
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/* CPU ID and Personality ID */
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#define MCU_BOARD_ID_REG 0x68
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#define MXC_MAX_EXP_IO_LINES 16
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/* interrupts like external uart , external ethernet etc*/
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#define EXPIO_INT_ENET 0
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#define EXPIO_INT_XUART_A 1
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#define EXPIO_INT_XUART_B 2
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#define EXPIO_INT_BUTTON_A 3
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#define EXPIO_INT_BUTTON_B 4
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static void __iomem *brd_io;
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static struct irq_domain *domain;
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static struct resource smsc911x_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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} , {
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct smsc911x_platform_config smsc911x_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
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};
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static struct platform_device smsc_lan9217_device = {
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.name = "smsc911x",
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.id = -1,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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};
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static void mxc_expio_irq_handler(struct irq_desc *desc)
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{
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u32 imr_val;
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u32 int_valid;
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u32 expio_irq;
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/* irq = gpio irq number */
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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imr_val = imx_readw(brd_io + INTR_MASK_REG);
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int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
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expio_irq = 0;
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for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
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if ((int_valid & 1) == 0)
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continue;
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generic_handle_irq(irq_find_mapping(domain, expio_irq));
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}
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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}
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/*
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* Disable an expio pin's interrupt by setting the bit in the imr.
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* Irq is an expio virtual irq number
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*/
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static void expio_mask_irq(struct irq_data *d)
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{
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u16 reg;
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u32 expio = d->hwirq;
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reg = imx_readw(brd_io + INTR_MASK_REG);
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reg |= (1 << expio);
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imx_writew(reg, brd_io + INTR_MASK_REG);
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}
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static void expio_ack_irq(struct irq_data *d)
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{
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u32 expio = d->hwirq;
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imx_writew(1 << expio, brd_io + INTR_RESET_REG);
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imx_writew(0, brd_io + INTR_RESET_REG);
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expio_mask_irq(d);
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}
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static void expio_unmask_irq(struct irq_data *d)
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{
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u16 reg;
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u32 expio = d->hwirq;
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reg = imx_readw(brd_io + INTR_MASK_REG);
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reg &= ~(1 << expio);
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imx_writew(reg, brd_io + INTR_MASK_REG);
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}
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static struct irq_chip expio_irq_chip = {
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.irq_ack = expio_ack_irq,
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.irq_mask = expio_mask_irq,
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.irq_unmask = expio_unmask_irq,
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};
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static struct regulator_consumer_supply dummy_supplies[] = {
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REGULATOR_SUPPLY("vdd33a", "smsc911x"),
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REGULATOR_SUPPLY("vddvario", "smsc911x"),
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};
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int __init mxc_expio_init(u32 base, u32 intr_gpio)
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{
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u32 p_irq = gpio_to_irq(intr_gpio);
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int irq_base;
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int i;
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brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
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if (brd_io == NULL)
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return -ENOMEM;
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if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
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(imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
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(imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
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pr_info("3-Stack Debug board not detected\n");
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iounmap(brd_io);
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brd_io = NULL;
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return -ENODEV;
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}
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pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
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readw(brd_io + CPLD_CODE_VER_REG));
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/*
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* Configure INT line as GPIO input
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*/
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gpio_request(intr_gpio, "expio_pirq");
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gpio_direction_input(intr_gpio);
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/* disable the interrupt and clear the status */
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imx_writew(0, brd_io + INTR_MASK_REG);
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imx_writew(0xFFFF, brd_io + INTR_RESET_REG);
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imx_writew(0, brd_io + INTR_RESET_REG);
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imx_writew(0x1F, brd_io + INTR_MASK_REG);
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irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
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WARN_ON(irq_base < 0);
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domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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WARN_ON(!domain);
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for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
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irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
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irq_clear_status_flags(i, IRQ_NOREQUEST);
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}
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irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
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irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
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/* Register Lan device on the debugboard */
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regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
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smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
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smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
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smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
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smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
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platform_device_register(&smsc_lan9217_device);
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return 0;
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}
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@ -1,11 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __ASM_ARCH_MXC_3DS_DB_H__
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#define __ASM_ARCH_MXC_3DS_DB_H__
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extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
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#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* Based on code for mobots boards,
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* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
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*/
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#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
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#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
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#ifndef __ASSEMBLY__
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enum mx31lilly_boards {
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MX31LILLY_NOBOARD = 0,
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MX31LILLY_DB = 1,
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};
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/*
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* This CPU module needs a baseboard to work. After basic initializing
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* its own devices, it calls the baseboard's init function.
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*/
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extern void mx31lilly_db_init(void);
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#endif
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#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */
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@ -1,29 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* Based on code for mobots boards,
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* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
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*/
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#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
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#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
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#ifndef __ASSEMBLY__
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enum mx31lite_boards {
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MX31LITE_NOBOARD = 0,
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MX31LITE_DB = 1,
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};
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/*
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* This CPU module needs a baseboard to work. After basic initializing
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* its own devices, it calls the baseboard's init function.
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*/
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extern void mx31lite_db_init(void);
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#endif
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#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
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*/
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#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
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#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
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#ifndef __ASSEMBLY__
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enum mx31moboard_boards {
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MX31NOBOARD = 0,
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MX31DEVBOARD = 1,
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MX31MARXBOT = 2,
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MX31SMARTBOT = 3,
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MX31EYEBOT = 4,
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};
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/*
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* This CPU module needs a baseboard to work. After basic initializing
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* its own devices, it calls the baseboard's init function.
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*/
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extern void mx31moboard_devboard_init(void);
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extern void mx31moboard_marxbot_init(void);
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extern void mx31moboard_smartbot_init(int board);
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#endif
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#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
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@ -1,579 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/memory.h>
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#include <asm/mach/map.h>
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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#include <linux/mfd/wm8350/audio.h>
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#include <linux/mfd/wm8350/core.h>
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#include <linux/mfd/wm8350/pmic.h>
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#endif
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#include "common.h"
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#include "devices-imx31.h"
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#include "hardware.h"
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#include "iomux-mx3.h"
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/* Base address of PBC controller */
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#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
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/* PBC Board interrupt status register */
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#define PBC_INTSTATUS 0x000016
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/* PBC Board interrupt current status register */
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#define PBC_INTCURR_STATUS 0x000018
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/* PBC Interrupt mask register set address */
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#define PBC_INTMASK_SET 0x00001A
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/* PBC Interrupt mask register clear address */
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#define PBC_INTMASK_CLEAR 0x00001C
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/* External UART A */
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#define PBC_SC16C652_UARTA 0x010000
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/* External UART B */
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#define PBC_SC16C652_UARTB 0x010010
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#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
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#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
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#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
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#define EXPIO_INT_XUART_INTA 10
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#define EXPIO_INT_XUART_INTB 11
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#define MXC_MAX_EXP_IO_LINES 16
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/* CS8900 */
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#define EXPIO_INT_ENET_INT 8
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#define CS4_CS8900_MMIO_START 0x20000
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static struct irq_domain *domain;
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/*
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* The serial port definition structure.
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*/
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
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.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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}, {
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
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.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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},
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{},
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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static struct resource mx31ads_cs8900_resources[] __initdata = {
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DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
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DEFINE_RES_IRQ(-1),
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};
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static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
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.name = "cs89x0",
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.id = 0,
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.res = mx31ads_cs8900_resources,
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.num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
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};
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static int __init mxc_init_extuart(void)
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{
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serial_platform_data[0].irq = irq_find_mapping(domain,
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EXPIO_INT_XUART_INTA);
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serial_platform_data[1].irq = irq_find_mapping(domain,
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EXPIO_INT_XUART_INTB);
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return platform_device_register(&serial_device);
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}
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static void __init mxc_init_ext_ethernet(void)
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{
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mx31ads_cs8900_resources[1].start =
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irq_find_mapping(domain, EXPIO_INT_ENET_INT);
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mx31ads_cs8900_resources[1].end =
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irq_find_mapping(domain, EXPIO_INT_ENET_INT);
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platform_device_register_full(
|
||||
(struct platform_device_info *)&mx31ads_cs8900_devinfo);
|
||||
}
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static unsigned int uart_pins[] = {
|
||||
MX31_PIN_CTS1__CTS1,
|
||||
MX31_PIN_RTS1__RTS1,
|
||||
MX31_PIN_TXD1__TXD1,
|
||||
MX31_PIN_RXD1__RXD1
|
||||
};
|
||||
|
||||
static inline void mxc_init_imx_uart(void)
|
||||
{
|
||||
mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
|
||||
imx31_add_imx_uart0(&uart_pdata);
|
||||
}
|
||||
|
||||
static void mx31ads_expio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
u32 imr_val;
|
||||
u32 int_valid;
|
||||
u32 expio_irq;
|
||||
|
||||
imr_val = imx_readw(PBC_INTMASK_SET_REG);
|
||||
int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
|
||||
|
||||
expio_irq = 0;
|
||||
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
|
||||
if ((int_valid & 1) == 0)
|
||||
continue;
|
||||
|
||||
generic_handle_irq(irq_find_mapping(domain, expio_irq));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable an expio pin's interrupt by setting the bit in the imr.
|
||||
* @param d an expio virtual irq description
|
||||
*/
|
||||
static void expio_mask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 expio = d->hwirq;
|
||||
/* mask the interrupt */
|
||||
imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
|
||||
imx_readw(PBC_INTMASK_CLEAR_REG);
|
||||
}
|
||||
|
||||
/*
|
||||
* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
|
||||
* @param d an expio virtual irq description
|
||||
*/
|
||||
static void expio_ack_irq(struct irq_data *d)
|
||||
{
|
||||
u32 expio = d->hwirq;
|
||||
/* clear the interrupt status */
|
||||
imx_writew(1 << expio, PBC_INTSTATUS_REG);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable a expio pin's interrupt by clearing the bit in the imr.
|
||||
* @param d an expio virtual irq description
|
||||
*/
|
||||
static void expio_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 expio = d->hwirq;
|
||||
/* unmask the interrupt */
|
||||
imx_writew(1 << expio, PBC_INTMASK_SET_REG);
|
||||
}
|
||||
|
||||
static struct irq_chip expio_irq_chip = {
|
||||
.name = "EXPIO(CPLD)",
|
||||
.irq_ack = expio_ack_irq,
|
||||
.irq_mask = expio_mask_irq,
|
||||
.irq_unmask = expio_unmask_irq,
|
||||
};
|
||||
|
||||
static void __init mx31ads_init_expio(void)
|
||||
{
|
||||
int irq_base;
|
||||
int i, irq;
|
||||
|
||||
printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
|
||||
|
||||
/*
|
||||
* Configure INT line as GPIO input
|
||||
*/
|
||||
mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
|
||||
|
||||
/* disable the interrupt and clear the status */
|
||||
imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
|
||||
imx_writew(0xFFFF, PBC_INTSTATUS_REG);
|
||||
|
||||
irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
|
||||
WARN_ON(irq_base < 0);
|
||||
|
||||
domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
|
||||
&irq_domain_simple_ops, NULL);
|
||||
WARN_ON(!domain);
|
||||
|
||||
for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
|
||||
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
|
||||
irq_clear_status_flags(i, IRQ_NOREQUEST);
|
||||
}
|
||||
irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
|
||||
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
|
||||
irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
|
||||
/* This section defines setup for the Wolfson Microelectronics
|
||||
* 1133-EV1 PMU/audio board. When other PMU boards are supported the
|
||||
* regulator definitions may be shared with them, but for now they can
|
||||
* only be used with this board so would generate warnings about
|
||||
* unused statics and some of the configuration is specific to this
|
||||
* module.
|
||||
*/
|
||||
|
||||
/* CPU */
|
||||
static struct regulator_consumer_supply sw1a_consumers[] = {
|
||||
{
|
||||
.supply = "cpu_vcc",
|
||||
}
|
||||
};
|
||||
|
||||
static struct regulator_init_data sw1a_data = {
|
||||
.constraints = {
|
||||
.name = "SW1A",
|
||||
.min_uV = 1275000,
|
||||
.max_uV = 1600000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_MODE,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL |
|
||||
REGULATOR_MODE_FAST,
|
||||
.state_mem = {
|
||||
.uV = 1400000,
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 1,
|
||||
},
|
||||
.initial_state = PM_SUSPEND_MEM,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
|
||||
.consumer_supplies = sw1a_consumers,
|
||||
};
|
||||
|
||||
/* System IO - High */
|
||||
static struct regulator_init_data viohi_data = {
|
||||
.constraints = {
|
||||
.name = "VIOHO",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.state_mem = {
|
||||
.uV = 2800000,
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 1,
|
||||
},
|
||||
.initial_state = PM_SUSPEND_MEM,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* System IO - Low */
|
||||
static struct regulator_init_data violo_data = {
|
||||
.constraints = {
|
||||
.name = "VIOLO",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.state_mem = {
|
||||
.uV = 1800000,
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 1,
|
||||
},
|
||||
.initial_state = PM_SUSPEND_MEM,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* DDR RAM */
|
||||
static struct regulator_init_data sw2a_data = {
|
||||
.constraints = {
|
||||
.name = "SW2A",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.state_mem = {
|
||||
.uV = 1800000,
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 1,
|
||||
},
|
||||
.state_disk = {
|
||||
.mode = REGULATOR_MODE_NORMAL,
|
||||
.enabled = 0,
|
||||
},
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
.initial_state = PM_SUSPEND_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data ldo1_data = {
|
||||
.constraints = {
|
||||
.name = "VCAM/VMMC1/VMMC2",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply ldo2_consumers[] = {
|
||||
{ .supply = "AVDD", .dev_name = "1-001a" },
|
||||
{ .supply = "HPVDD", .dev_name = "1-001a" },
|
||||
};
|
||||
|
||||
/* CODEC and SIM */
|
||||
static struct regulator_init_data ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "VESIM/VSIM/AVDD",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
|
||||
.consumer_supplies = ldo2_consumers,
|
||||
};
|
||||
|
||||
/* General */
|
||||
static struct regulator_init_data vdig_data = {
|
||||
.constraints = {
|
||||
.name = "VDIG",
|
||||
.min_uV = 1500000,
|
||||
.max_uV = 1500000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Tranceivers */
|
||||
static struct regulator_init_data ldo4_data = {
|
||||
.constraints = {
|
||||
.name = "VRF1/CVDD_2.775",
|
||||
.min_uV = 2500000,
|
||||
.max_uV = 2500000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct wm8350_led_platform_data wm8350_led_data = {
|
||||
.name = "wm8350:white",
|
||||
.default_trigger = "heartbeat",
|
||||
.max_uA = 27899,
|
||||
};
|
||||
|
||||
static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
|
||||
.vmid_discharge_msecs = 1000,
|
||||
.drain_msecs = 30,
|
||||
.cap_discharge_msecs = 700,
|
||||
.vmid_charge_msecs = 700,
|
||||
.vmid_s_curve = WM8350_S_CURVE_SLOW,
|
||||
.dis_out4 = WM8350_DISCHARGE_SLOW,
|
||||
.dis_out3 = WM8350_DISCHARGE_SLOW,
|
||||
.dis_out2 = WM8350_DISCHARGE_SLOW,
|
||||
.dis_out1 = WM8350_DISCHARGE_SLOW,
|
||||
.vroi_out4 = WM8350_TIE_OFF_500R,
|
||||
.vroi_out3 = WM8350_TIE_OFF_500R,
|
||||
.vroi_out2 = WM8350_TIE_OFF_500R,
|
||||
.vroi_out1 = WM8350_TIE_OFF_500R,
|
||||
.vroi_enable = 0,
|
||||
.codec_current_on = WM8350_CODEC_ISEL_1_0,
|
||||
.codec_current_standby = WM8350_CODEC_ISEL_0_5,
|
||||
.codec_current_charge = WM8350_CODEC_ISEL_1_5,
|
||||
};
|
||||
|
||||
static int mx31_wm8350_init(struct wm8350 *wm8350)
|
||||
{
|
||||
wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
|
||||
WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
|
||||
WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_ON);
|
||||
|
||||
wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
|
||||
WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
|
||||
WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_ON);
|
||||
|
||||
wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
|
||||
WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
|
||||
WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_OFF);
|
||||
|
||||
wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
|
||||
WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
|
||||
WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_OFF);
|
||||
|
||||
wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
|
||||
WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
|
||||
WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_OFF);
|
||||
|
||||
wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
|
||||
WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
|
||||
WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_OFF);
|
||||
|
||||
wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
|
||||
WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
|
||||
WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
|
||||
WM8350_GPIO_DEBOUNCE_OFF);
|
||||
|
||||
wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
|
||||
wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
|
||||
|
||||
/* LEDs */
|
||||
wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
|
||||
WM8350_DC5_ERRACT_SHUTDOWN_CONV);
|
||||
wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
|
||||
WM8350_ISINK_FLASH_DISABLE,
|
||||
WM8350_ISINK_FLASH_TRIG_BIT,
|
||||
WM8350_ISINK_FLASH_DUR_32MS,
|
||||
WM8350_ISINK_FLASH_ON_INSTANT,
|
||||
WM8350_ISINK_FLASH_OFF_INSTANT,
|
||||
WM8350_ISINK_FLASH_MODE_EN);
|
||||
wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
|
||||
WM8350_ISINK_MODE_BOOST,
|
||||
WM8350_ISINK_ILIM_NORMAL,
|
||||
WM8350_DC5_RMP_20V,
|
||||
WM8350_DC5_FBSRC_ISINKA);
|
||||
wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
|
||||
&wm8350_led_data);
|
||||
|
||||
wm8350->codec.platform_data = &imx32ads_wm8350_setup;
|
||||
|
||||
regulator_has_full_constraints();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
|
||||
.init = mx31_wm8350_init,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
|
||||
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
|
||||
{
|
||||
I2C_BOARD_INFO("wm8350", 0x1a),
|
||||
.platform_data = &mx31_wm8350_pdata,
|
||||
/* irq number is run-time assigned */
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static void __init mxc_init_i2c(void)
|
||||
{
|
||||
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
|
||||
mx31ads_i2c1_devices[0].irq =
|
||||
gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
|
||||
#endif
|
||||
i2c_register_board_info(1, mx31ads_i2c1_devices,
|
||||
ARRAY_SIZE(mx31ads_i2c1_devices));
|
||||
|
||||
mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
|
||||
mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
|
||||
|
||||
imx31_add_imx_i2c1(NULL);
|
||||
}
|
||||
|
||||
static unsigned int ssi_pins[] = {
|
||||
MX31_PIN_SFS5__SFS5,
|
||||
MX31_PIN_SCK5__SCK5,
|
||||
MX31_PIN_SRXD5__SRXD5,
|
||||
MX31_PIN_STXD5__STXD5,
|
||||
};
|
||||
|
||||
static void __init mxc_init_audio(void)
|
||||
{
|
||||
imx31_add_imx_ssi(0, NULL);
|
||||
mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
|
||||
}
|
||||
|
||||
/*
|
||||
* Static mappings, starting from the CS4 start address up to the start address
|
||||
* of the CS8900.
|
||||
*/
|
||||
static struct map_desc mx31ads_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
|
||||
.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
|
||||
.length = CS4_CS8900_MMIO_START,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
static void __init mx31ads_map_io(void)
|
||||
{
|
||||
mx31_map_io();
|
||||
iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
|
||||
}
|
||||
|
||||
static void __init mx31ads_init(void)
|
||||
{
|
||||
imx31_soc_init();
|
||||
|
||||
mxc_init_imx_uart();
|
||||
mxc_init_audio();
|
||||
}
|
||||
|
||||
static void __init mx31ads_late(void)
|
||||
{
|
||||
mx31ads_init_expio();
|
||||
mxc_init_extuart();
|
||||
mxc_init_i2c();
|
||||
mxc_init_ext_ethernet();
|
||||
}
|
||||
|
||||
static void __init mx31ads_timer_init(void)
|
||||
{
|
||||
mx31_clocks_init(26000000);
|
||||
}
|
||||
|
||||
MACHINE_START(MX31ADS, "Freescale MX31ADS")
|
||||
/* Maintainer: Freescale Semiconductor, Inc. */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx31ads_map_io,
|
||||
.init_early = imx31_init_early,
|
||||
.init_irq = mx31_init_irq,
|
||||
.init_time = mx31ads_timer_init,
|
||||
.init_machine = mx31ads_init,
|
||||
.init_late = mx31ads_late,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* LogicPD i.MX31 SOM-LV development board support
|
||||
*
|
||||
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
|
||||
*
|
||||
* based on code for other MX31 boards,
|
||||
*
|
||||
* Copyright 2005-2007 Freescale Semiconductor
|
||||
* Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
|
||||
* Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "board-mx31lite.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
|
||||
/*
|
||||
* This file contains board-specific initialization routines for the
|
||||
* LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
|
||||
* If you design an own baseboard for the module, use this file as base
|
||||
* for support code.
|
||||
*/
|
||||
|
||||
static unsigned int litekit_db_board_pins[] __initdata = {
|
||||
/* SDHC1 */
|
||||
MX31_PIN_SD1_DATA0__SD1_DATA0,
|
||||
MX31_PIN_SD1_DATA1__SD1_DATA1,
|
||||
MX31_PIN_SD1_DATA2__SD1_DATA2,
|
||||
MX31_PIN_SD1_DATA3__SD1_DATA3,
|
||||
MX31_PIN_SD1_CLK__SD1_CLK,
|
||||
MX31_PIN_SD1_CMD__SD1_CMD,
|
||||
};
|
||||
|
||||
/* MMC */
|
||||
|
||||
static int gpio_det, gpio_wp;
|
||||
|
||||
#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_ODE_CMOS)
|
||||
|
||||
static int mxc_mmc1_get_ro(struct device *dev)
|
||||
{
|
||||
return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
|
||||
}
|
||||
|
||||
static int mxc_mmc1_init(struct device *dev,
|
||||
irq_handler_t detect_irq, void *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
|
||||
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
|
||||
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
|
||||
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
|
||||
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
|
||||
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
|
||||
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
|
||||
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
|
||||
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
|
||||
|
||||
ret = gpio_request(gpio_det, "MMC detect");
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = gpio_request(gpio_wp, "MMC w/p");
|
||||
if (ret)
|
||||
goto exit_free_det;
|
||||
|
||||
gpio_direction_input(gpio_det);
|
||||
gpio_direction_input(gpio_wp);
|
||||
|
||||
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
|
||||
detect_irq,
|
||||
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
|
||||
"MMC detect", data);
|
||||
if (ret)
|
||||
goto exit_free_wp;
|
||||
|
||||
return 0;
|
||||
|
||||
exit_free_wp:
|
||||
gpio_free(gpio_wp);
|
||||
|
||||
exit_free_det:
|
||||
gpio_free(gpio_det);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mxc_mmc1_exit(struct device *dev, void *data)
|
||||
{
|
||||
gpio_free(gpio_det);
|
||||
gpio_free(gpio_wp);
|
||||
free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
|
||||
}
|
||||
|
||||
static const struct imxmmc_platform_data mmc_pdata __initconst = {
|
||||
.get_ro = mxc_mmc1_get_ro,
|
||||
.init = mxc_mmc1_init,
|
||||
.exit = mxc_mmc1_exit,
|
||||
};
|
||||
|
||||
/* GPIO LEDs */
|
||||
|
||||
static const struct gpio_led litekit_leds[] __initconst = {
|
||||
{
|
||||
.name = "GPIO0",
|
||||
.gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
|
||||
.active_low = 1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
},
|
||||
{
|
||||
.name = "GPIO1",
|
||||
.gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
|
||||
.active_low = 1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data
|
||||
litekit_led_platform_data __initconst = {
|
||||
.leds = litekit_leds,
|
||||
.num_leds = ARRAY_SIZE(litekit_leds),
|
||||
};
|
||||
|
||||
void __init mx31lite_db_init(void)
|
||||
{
|
||||
mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
|
||||
ARRAY_SIZE(litekit_db_board_pins),
|
||||
"development board pins");
|
||||
imx31_add_mxc_mmc(0, &mmc_pdata);
|
||||
gpio_led_register_device(-1, &litekit_led_platform_data);
|
||||
imx31_add_imx2_wdt();
|
||||
imx31_add_mxc_rtc();
|
||||
}
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __PCM037_H__
|
||||
#define __PCM037_H__
|
||||
|
||||
enum pcm037_board_variant {
|
||||
PCM037_PCM970,
|
||||
PCM037_EET,
|
||||
};
|
||||
|
||||
extern enum pcm037_board_variant pcm037_variant(void);
|
||||
|
||||
#ifdef CONFIG_MACH_PCM037_EET
|
||||
int pcm037_eet_init_devices(void);
|
||||
#else
|
||||
static inline int pcm037_eet_init_devices(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue