mirror of https://gitee.com/openkylin/linux.git
drm/radeon/kms: add LTE/GTE discard + rv515 two sided stencil register.
This adds some rv350+ register for LTE/GTE discard, and enables the rv515 two sided stencil register. It also disables the DEPTHXY_OFFSET register which can be used to workaround the CS checker. Moves rs690 to proper place in rs600 and uses correct table on rs600. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
e07cccf404
commit
a54775c875
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@ -995,7 +995,7 @@ static const unsigned r300_reg_safe_bm[159] = {
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
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0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x0003FC01, 0xFFFFFFF8, 0xFE800B19,
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0x0003FC01, 0xFFFFFCF8, 0xFF800B19,
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};
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};
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static int r300_packet0_check(struct radeon_cs_parser *p,
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static int r300_packet0_check(struct radeon_cs_parser *p,
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@ -266,6 +266,7 @@ static struct radeon_asic rs400_asic = {
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/*
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/*
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* rs600.
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* rs600.
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*/
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*/
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int rs600_init(struct radeon_device *dev);
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void rs600_errata(struct radeon_device *rdev);
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void rs600_errata(struct radeon_device *rdev);
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void rs600_vram_info(struct radeon_device *rdev);
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void rs600_vram_info(struct radeon_device *rdev);
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int rs600_mc_init(struct radeon_device *rdev);
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int rs600_mc_init(struct radeon_device *rdev);
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@ -281,7 +282,7 @@ uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs600_bandwidth_update(struct radeon_device *rdev);
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void rs600_bandwidth_update(struct radeon_device *rdev);
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static struct radeon_asic rs600_asic = {
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static struct radeon_asic rs600_asic = {
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.init = &r300_init,
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.init = &rs600_init,
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.errata = &rs600_errata,
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.errata = &rs600_errata,
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.vram_info = &rs600_vram_info,
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.vram_info = &rs600_vram_info,
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.gpu_reset = &r300_gpu_reset,
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.gpu_reset = &r300_gpu_reset,
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@ -316,7 +317,6 @@ static struct radeon_asic rs600_asic = {
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/*
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/*
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* rs690,rs740
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* rs690,rs740
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*/
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*/
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int rs690_init(struct radeon_device *rdev);
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void rs690_errata(struct radeon_device *rdev);
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void rs690_errata(struct radeon_device *rdev);
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void rs690_vram_info(struct radeon_device *rdev);
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void rs690_vram_info(struct radeon_device *rdev);
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int rs690_mc_init(struct radeon_device *rdev);
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int rs690_mc_init(struct radeon_device *rdev);
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@ -325,7 +325,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs690_bandwidth_update(struct radeon_device *rdev);
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void rs690_bandwidth_update(struct radeon_device *rdev);
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static struct radeon_asic rs690_asic = {
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static struct radeon_asic rs690_asic = {
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.init = &rs690_init,
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.init = &rs600_init,
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.errata = &rs690_errata,
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.errata = &rs690_errata,
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.vram_info = &rs690_vram_info,
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.vram_info = &rs690_vram_info,
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.gpu_reset = &r300_gpu_reset,
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.gpu_reset = &r300_gpu_reset,
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@ -409,3 +409,68 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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((reg) & RS600_MC_ADDR_MASK));
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((reg) & RS600_MC_ADDR_MASK));
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WREG32(RS600_MC_DATA, v);
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WREG32(RS600_MC_DATA, v);
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}
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}
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static const unsigned rs600_reg_safe_bm[219] = {
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
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0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
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0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
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0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
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0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
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0x00000000, 0x0000C100, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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};
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int rs600_init(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
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return 0;
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}
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@ -653,67 +653,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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}
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}
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static const unsigned rs690_reg_safe_bm[219] = {
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF,
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0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000,
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0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF,
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0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF,
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0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,
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0x00000000,0x0000C100,0x00000000,0x00000000,
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0x00000000,0x00000000,0x00000000,0x00000000,
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0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF,
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0x00000000,0x00000000,0x00000000,0x00000000,
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0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
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};
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int rs690_init(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm);
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return 0;
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}
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@ -508,7 +508,7 @@ static const unsigned r500_reg_safe_bm[219] = {
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF,
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0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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