mirror of https://gitee.com/openkylin/linux.git
drm/i915: s/dpio_lock/sb_lock/
Rename dpio_lock to sb_lock to inform the reader that its primary purpose is to protect the sideband mailbox rather than some DPIO state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
parent
b12ce1d84f
commit
a580516d9f
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@ -814,7 +814,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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spin_lock_init(&dev_priv->uncore.lock);
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spin_lock_init(&dev_priv->mm.object_stat_lock);
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spin_lock_init(&dev_priv->mmio_flip_lock);
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mutex_init(&dev_priv->dpio_lock);
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mutex_init(&dev_priv->sb_lock);
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mutex_init(&dev_priv->modeset_restore_lock);
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mutex_init(&dev_priv->csr_lock);
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@ -1666,8 +1666,8 @@ struct drm_i915_private {
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/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
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struct pm_qos_request pm_qos;
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/* DPIO indirect register protection */
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struct mutex dpio_lock;
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/* Sideband mailbox protection */
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struct mutex sb_lock;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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union {
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@ -1140,9 +1140,9 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
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u32 val;
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bool cur_state;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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cur_state = val & DSI_PLL_VCO_EN;
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I915_STATE_WARN(cur_state != state,
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@ -1661,7 +1661,7 @@ static void chv_enable_pll(struct intel_crtc *crtc,
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BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* Enable back the 10bit clock to display controller */
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tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
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@ -1684,7 +1684,7 @@ static void chv_enable_pll(struct intel_crtc *crtc,
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I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
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POSTING_READ(DPLL_MD(pipe));
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static int intel_num_dvo_pipes(struct drm_device *dev)
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@ -1826,7 +1826,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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I915_WRITE(DPLL(pipe), val);
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POSTING_READ(DPLL(pipe));
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* Disable 10bit clock to display controller */
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val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
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@ -1844,7 +1844,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
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}
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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@ -3939,7 +3939,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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u32 divsel, phaseinc, auxdiv, phasedir = 0;
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u32 temp;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* It is necessary to ungate the pixclk gate prior to programming
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* the divisors, and gate it back when it is done.
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@ -4016,7 +4016,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
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@ -5728,10 +5728,10 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
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int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
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/* Obtain SKU information */
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
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CCK_FUSE_HPLL_FREQ_MASK;
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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return vco_freq[hpll_freq] * 1000;
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}
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@ -5785,7 +5785,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
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divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* adjust cdclk divider */
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val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
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val &= ~DISPLAY_FREQUENCY_VALUES;
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@ -5796,10 +5796,10 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
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DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
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50))
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DRM_ERROR("timed out waiting for CDclk change\n");
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* adjust self-refresh exit latency value */
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val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
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val &= ~0x7f;
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@ -5813,7 +5813,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
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else
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val |= 3000 / 250; /* 3.0 usec */
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vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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vlv_update_cdclk(dev);
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}
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@ -6741,9 +6741,9 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
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if (dev_priv->hpll_freq == 0)
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dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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divider = val & DISPLAY_FREQUENCY_VALUES;
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@ -7085,7 +7085,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
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u32 bestn, bestm1, bestm2, bestp1, bestp2;
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u32 coreclk, reg_val;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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bestn = pipe_config->dpll.n;
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bestm1 = pipe_config->dpll.m1;
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@ -7163,7 +7163,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void chv_update_pll(struct intel_crtc *crtc,
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@ -7208,7 +7208,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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I915_WRITE(dpll_reg,
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pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* p1 and p2 divider */
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vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
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@ -7281,7 +7281,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
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DPIO_AFC_RECAL);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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/**
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@ -7782,9 +7782,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
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if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
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return;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
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clock.m2 = mdiv & DPIO_M2DIV_MASK;
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@ -7878,12 +7878,12 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
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u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
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int refclk = 100000;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
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pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
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pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
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pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
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clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
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@ -8249,7 +8249,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
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with_fdi, "LP PCH doesn't have FDI\n"))
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with_fdi = false;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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tmp &= ~SBI_SSCCTL_DISABLE;
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@ -8275,7 +8275,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
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tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
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intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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/* Sequence to disable CLKOUT_DP */
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@ -8284,7 +8284,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t reg, tmp;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
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SBI_GEN0 : SBI_DBUFF0;
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@ -8303,7 +8303,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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}
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void lpt_init_pch_refclk(struct drm_device *dev)
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@ -2355,7 +2355,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
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intel_dp_link_down(intel_dp);
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* Propagate soft reset to data lane reset */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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@ -2374,7 +2374,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
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val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void
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@ -2671,7 +2671,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
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int pipe = intel_crtc->pipe;
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u32 val;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
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val = 0;
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@ -2684,7 +2684,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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intel_enable_dp(encoder);
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}
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@ -2702,7 +2702,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
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intel_dp_prepare(encoder);
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/* Program Tx lane resets to default */
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
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DPIO_PCS_TX_LANE2_RESET |
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DPIO_PCS_TX_LANE1_RESET);
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@ -2716,7 +2716,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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static void chv_pre_enable_dp(struct intel_encoder *encoder)
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@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
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int data, i, stagger;
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u32 val;
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* allow hardware to manage TX FIFO reset source */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
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@ -2802,7 +2802,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
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DPIO_TX1_STAGGER_MULT(7) |
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DPIO_TX2_STAGGER_MULT(5));
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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intel_enable_dp(encoder);
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}
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@ -2820,7 +2820,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
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intel_dp_prepare(encoder);
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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/* program left/right clock distribution */
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if (pipe != PIPE_B) {
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@ -2870,7 +2870,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
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val |= CHV_CMN_USEDCLKCHANNEL;
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vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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}
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/*
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@ -3095,7 +3095,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
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@ -3104,7 +3104,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
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vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
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mutex_unlock(&dev_priv->dpio_lock);
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mutex_unlock(&dev_priv->sb_lock);
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return 0;
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}
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@ -3191,7 +3191,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->sb_lock);
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|
||||
/* Clear calc init */
|
||||
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
|
||||
|
|
@ -3278,7 +3278,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
|
|||
val |= DPIO_LRC_BYPASS;
|
||||
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -239,7 +239,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
|
|||
|
||||
static void band_gap_reset(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
|
||||
vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
|
||||
|
|
@ -248,7 +248,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
|
|||
vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
|
||||
vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
|
||||
|
|
@ -346,11 +346,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
|
|||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
|
||||
* needed everytime after power gate */
|
||||
vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
/* bandgap reset is needed after everytime we do power gate */
|
||||
band_gap_reset(dev_priv);
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
|
|||
function = gtable[gpio].function_reg;
|
||||
pad = gtable[gpio].pad_reg;
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
if (!gtable[gpio].init) {
|
||||
/* program the function */
|
||||
/* FIXME: remove constant below */
|
||||
|
|
@ -224,7 +224,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
|
|||
|
||||
/* pull up/down */
|
||||
vlv_gpio_nc_write(dev_priv, pad, val);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
|
|||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
vlv_configure_dsi_pll(encoder);
|
||||
|
||||
|
|
@ -258,11 +258,11 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
|
|||
if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
|
||||
DSI_PLL_LOCK, 20)) {
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
DRM_ERROR("DSI PLL lock failed\n");
|
||||
return;
|
||||
}
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
DRM_DEBUG_KMS("DSI PLL locked\n");
|
||||
}
|
||||
|
|
@ -274,14 +274,14 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
|
|||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
|
||||
tmp &= ~DSI_PLL_VCO_EN;
|
||||
tmp |= DSI_PLL_LDO_GATE;
|
||||
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
|
||||
|
|
@ -319,10 +319,10 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
|
|||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
|
||||
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
/* mask out other bits and extract the P1 divisor */
|
||||
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
|
||||
|
|
|
|||
|
|
@ -1293,7 +1293,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
|
|||
u32 val;
|
||||
|
||||
/* Enable clock channels for this port */
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
|
||||
val = 0;
|
||||
if (pipe)
|
||||
|
|
@ -1316,7 +1316,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
|
|||
/* Program lane clock */
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
intel_hdmi->set_infoframes(&encoder->base,
|
||||
intel_crtc->config->has_hdmi_sink,
|
||||
|
|
@ -1340,7 +1340,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
|||
intel_hdmi_prepare(encoder);
|
||||
|
||||
/* Program Tx lane resets to default */
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
|
||||
DPIO_PCS_TX_LANE2_RESET |
|
||||
DPIO_PCS_TX_LANE1_RESET);
|
||||
|
|
@ -1357,7 +1357,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
|||
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
||||
|
|
@ -1373,7 +1373,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
|||
|
||||
intel_hdmi_prepare(encoder);
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
/* program left/right clock distribution */
|
||||
if (pipe != PIPE_B) {
|
||||
|
|
@ -1423,7 +1423,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
|||
val |= CHV_CMN_USEDCLKCHANNEL;
|
||||
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
|
||||
|
|
@ -1436,10 +1436,10 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
|
|||
int pipe = intel_crtc->pipe;
|
||||
|
||||
/* Reset lanes to avoid HDMI flicker (VLV w/a) */
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static void chv_hdmi_post_disable(struct intel_encoder *encoder)
|
||||
|
|
@ -1453,7 +1453,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
|
|||
enum pipe pipe = intel_crtc->pipe;
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
/* Propagate soft reset to data lane reset */
|
||||
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
|
||||
|
|
@ -1472,7 +1472,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
|
|||
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
||||
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
|
||||
|
|
@ -1490,7 +1490,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
|
|||
int data, i, stagger;
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
|
||||
/* allow hardware to manage TX FIFO reset source */
|
||||
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
|
||||
|
|
@ -1633,7 +1633,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
|
|||
val |= DPIO_LRC_BYPASS;
|
||||
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
|
||||
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
intel_hdmi->set_infoframes(&encoder->base,
|
||||
intel_crtc->config->has_hdmi_sink,
|
||||
|
|
|
|||
|
|
@ -4964,9 +4964,9 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
|
|||
|
||||
mutex_lock(&dev_priv->rps.hw_lock);
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
switch ((val >> 2) & 0x7) {
|
||||
case 0:
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
|
|||
(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
|
||||
(bar << IOSF_BAR_SHIFT);
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
|
||||
|
||||
if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
|
||||
DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
|
||||
|
|
@ -81,10 +81,10 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
|
|||
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
|
||||
SB_CRRDDA_NP, addr, &val);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
|
@ -93,10 +93,10 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
|
|||
{
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
|
||||
SB_CRWRDA_NP, addr, &val);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
}
|
||||
|
||||
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
|
||||
|
|
@ -121,10 +121,10 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
|
|||
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
||||
|
||||
mutex_lock(&dev_priv->dpio_lock);
|
||||
mutex_lock(&dev_priv->sb_lock);
|
||||
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
|
||||
SB_CRRDDA_NP, addr, &val);
|
||||
mutex_unlock(&dev_priv->dpio_lock);
|
||||
mutex_unlock(&dev_priv->sb_lock);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
|
@ -213,7 +213,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
|
|||
enum intel_sbi_destination destination)
|
||||
{
|
||||
u32 value = 0;
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
|
||||
|
||||
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
|
||||
100)) {
|
||||
|
|
@ -243,7 +243,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
|
|||
{
|
||||
u32 tmp;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
|
||||
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
|
||||
|
||||
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
|
||||
100)) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue