openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition 

n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode',
to comply with the SPI NOR int (*read_reg)() method. The 'const'
qualifier has no meaning for parameters passed by value, drop it.
Going furher, the opcode was passed to cqspi_calc_rdreg() and never used,
drop it.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
This commit is contained in:
Tudor Ambarus 2019-09-24 07:45:58 +00:00
parent 4539778753
commit a5c6603038
No known key found for this signature in database
GPG Key ID: 4B554F47A58D14E9
1 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/mtd/spi-nor/cadence-quadspi.c
View File

@ -285,7 +285,7 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode) static unsigned int cqspi_calc_rdreg(struct spi_nor *nor)
{ {
struct cqspi_flash_pdata *f_pdata = nor->priv; struct cqspi_flash_pdata *f_pdata = nor->priv;
u32 rdreg = 0; u32 rdreg = 0;
@ -354,8 +354,7 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
return cqspi_wait_idle(cqspi); return cqspi_wait_idle(cqspi);
} }
static int cqspi_command_read(struct spi_nor *nor, static int cqspi_command_read(struct spi_nor *nor, u8 opcode,
const u8 *txbuf, const unsigned n_tx,
u8 *rxbuf, size_t n_rx) u8 *rxbuf, size_t n_rx)
{ {
struct cqspi_flash_pdata *f_pdata = nor->priv; struct cqspi_flash_pdata *f_pdata = nor->priv;
@ -373,9 +372,9 @@ static int cqspi_command_read(struct spi_nor *nor,
return -EINVAL; return -EINVAL;
} }
reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
rdreg = cqspi_calc_rdreg(nor, txbuf[0]); rdreg = cqspi_calc_rdreg(nor);
writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@ -471,7 +470,7 @@ static int cqspi_read_setup(struct spi_nor *nor)
unsigned int reg; unsigned int reg;
reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
reg |= cqspi_calc_rdreg(nor, nor->read_opcode); reg |= cqspi_calc_rdreg(nor);
/* Setup dummy clock cycles */ /* Setup dummy clock cycles */
dummy_clk = nor->read_dummy; dummy_clk = nor->read_dummy;
@ -604,7 +603,7 @@ static int cqspi_write_setup(struct spi_nor *nor)
/* Set opcode. */ /* Set opcode. */
reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, reg_base + CQSPI_REG_WR_INSTR); writel(reg, reg_base + CQSPI_REG_WR_INSTR);
reg = cqspi_calc_rdreg(nor, nor->program_opcode); reg = cqspi_calc_rdreg(nor);
writel(reg, reg_base + CQSPI_REG_RD_INSTR); writel(reg, reg_base + CQSPI_REG_RD_INSTR);
reg = readl(reg_base + CQSPI_REG_SIZE); reg = readl(reg_base + CQSPI_REG_SIZE);
@ -1087,7 +1086,7 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
ret = cqspi_set_protocol(nor, 0); ret = cqspi_set_protocol(nor, 0);
if (!ret) if (!ret)
ret = cqspi_command_read(nor, &opcode, 1, buf, len); ret = cqspi_command_read(nor, opcode, buf, len);
return ret; return ret;
} }