mirror of https://gitee.com/openkylin/linux.git
media: atomisp: remove non-used 32-bits consts at system_local
There is an abstraction at the code in order to support 32 or 64 bits address/data length. However, for all Atom chipsets supported by this version, the size is fixed. So, cleanup the mess, removing the uused code and placing the data sizes on a single place. The end goal is to completely remove those local/global headers, replacing them by some ISP-version dependent struct, in order for the driver to decide what version it would need in runtime. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Mauro Carvalho Chehab
parent
ecf1b4ca97
commit
a6154805d0
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@ -52,32 +52,14 @@ typedef unsigned short hive_uint16;
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typedef unsigned int hive_uint32;
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typedef unsigned long long hive_uint64;
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/* by default assume 32 bit master port (both data and address) */
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#ifndef HRT_DATA_WIDTH
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#define HRT_DATA_WIDTH 32
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#endif
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#ifndef HRT_ADDRESS_WIDTH
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#define HRT_ADDRESS_WIDTH 32
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#endif
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#define HRT_DATA_WIDTH 32
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#define HRT_ADDRESS_WIDTH 64
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#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
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#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
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#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
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#if HRT_DATA_WIDTH == 64
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typedef hive_uint64 hrt_data;
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#elif HRT_DATA_WIDTH == 32
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typedef hive_uint32 hrt_data;
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#else
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#error data width not supported
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#endif
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#if HRT_ADDRESS_WIDTH == 64
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typedef hive_uint64 hrt_address;
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#elif HRT_ADDRESS_WIDTH == 32
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typedef hive_uint32 hrt_address;
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#else
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#error adddres width not supported
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#endif
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/* use 64 bit addresses in simulation, where possible */
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typedef hive_uint64 hive_sim_address;
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@ -75,8 +75,6 @@
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* Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
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*/
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#define HRT_VADDRESS_WIDTH 32
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//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/
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#define HRT_DATA_WIDTH 32
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#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
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#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
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@ -24,17 +24,12 @@
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#include "system_global.h"
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/* HRT assumes 32 by default (see Linux/include/hive_types.h), overrule it in case it is different */
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#undef HRT_ADDRESS_WIDTH
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#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
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/* This interface is deprecated */
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#include "hive_types.h"
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/*
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* Cell specific address maps
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*/
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#if HRT_ADDRESS_WIDTH == 64
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
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@ -154,130 +149,4 @@ static const hrt_address RX_BASE[N_RX_ID] = {
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(hrt_address)0x0000000000080100ULL
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};
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#elif HRT_ADDRESS_WIDTH == 32
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#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
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/* ISP */
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static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
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(hrt_address)0x00020000UL
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};
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static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
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(hrt_address)0x00200000UL
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};
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static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
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(hrt_address)0x100000UL
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};
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/* SP */
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static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
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(hrt_address)0x00010000UL
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};
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static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
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(hrt_address)0x00300000UL
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};
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/* MMU */
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/*
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* MMU0_ID: The data MMU
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* MMU1_ID: The icache MMU
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*/
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static const hrt_address MMU_BASE[N_MMU_ID] = {
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(hrt_address)0x00070000UL,
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(hrt_address)0x000A0000UL
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};
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/* DMA */
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static const hrt_address DMA_BASE[N_DMA_ID] = {
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(hrt_address)0x00040000UL
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};
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/* IRQ */
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static const hrt_address IRQ_BASE[N_IRQ_ID] = {
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(hrt_address)0x00000500UL,
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(hrt_address)0x00030A00UL,
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(hrt_address)0x0008C000UL,
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(hrt_address)0x00090200UL
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};
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/*
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(hrt_address)0x00000500UL};
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*/
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/* GDC */
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static const hrt_address GDC_BASE[N_GDC_ID] = {
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(hrt_address)0x00050000UL,
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(hrt_address)0x00060000UL
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};
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
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static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
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(hrt_address)0x00000000UL
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};
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/*
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static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
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(hrt_address)0x00000000UL};
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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(hrt_address)0x00090000UL};
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*/
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/* GP_DEVICE (single base for all separate GP_REG instances) */
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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(hrt_address)0x00000000UL
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};
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/*GP TIMER , all timer registers are inter-twined,
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* so, having multiple base addresses for
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* different timers does not help*/
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static const hrt_address GP_TIMER_BASE =
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(hrt_address)0x00000600UL;
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/* GPIO */
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static const hrt_address GPIO_BASE[N_GPIO_ID] = {
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(hrt_address)0x00000400UL
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};
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/* TIMED_CTRL */
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static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
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(hrt_address)0x00000100UL
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};
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/* INPUT_FORMATTER */
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static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
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(hrt_address)0x00030000UL,
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(hrt_address)0x00030200UL,
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(hrt_address)0x00030400UL
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};
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/* (hrt_address)0x00030600UL, */ /* memcpy() */
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/* INPUT_SYSTEM */
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static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
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(hrt_address)0x00080000UL
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};
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/* (hrt_address)0x00081000UL, */ /* capture A */
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/* (hrt_address)0x00082000UL, */ /* capture B */
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/* (hrt_address)0x00083000UL, */ /* capture C */
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/* (hrt_address)0x00084000UL, */ /* Acquisition */
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/* (hrt_address)0x00085000UL, */ /* DMA */
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/* (hrt_address)0x00089000UL, */ /* ctrl */
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/* (hrt_address)0x0008A000UL, */ /* GP regs */
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/* (hrt_address)0x0008B000UL, */ /* FIFO */
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/* (hrt_address)0x0008C000UL, */ /* IRQ */
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/* RX, the MIPI lane control regs start at offset 0 */
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static const hrt_address RX_BASE[N_RX_ID] = {
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(hrt_address)0x00080100UL
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};
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#else
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#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
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#endif
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#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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@ -85,11 +85,7 @@
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* the HRT types do not fully apply
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*/
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#define HRT_VADDRESS_WIDTH 32
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/* Surprise, this is a local property*/
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/*#define HRT_ADDRESS_WIDTH 64 */
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#define HRT_DATA_WIDTH 32
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#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
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#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
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/* The main bus connecting all devices */
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@ -24,15 +24,12 @@
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#include "system_global.h"
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#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
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/* This interface is deprecated */
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#include "hive_types.h"
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/*
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* Cell specific address maps
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*/
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#if HRT_ADDRESS_WIDTH == 64
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
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@ -198,175 +195,5 @@ static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
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0x00000000000C2C00ULL, /* stream2mmio controller B */
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0x00000000000C4C00ULL /* stream2mmio controller C */
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};
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#elif HRT_ADDRESS_WIDTH == 32
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#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
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/* ISP */
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static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
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0x00020000UL
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};
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static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
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0xffffffffUL
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};
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static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
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0xffffffffUL
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};
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/* SP */
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static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
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0x00010000UL
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};
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static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
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0x00300000UL
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};
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/* MMU */
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/*
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* MMU0_ID: The data MMU
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* MMU1_ID: The icache MMU
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*/
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static const hrt_address MMU_BASE[N_MMU_ID] = {
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0x00070000UL,
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0x000A0000UL
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};
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/* DMA */
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static const hrt_address DMA_BASE[N_DMA_ID] = {
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0x00040000UL
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};
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static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
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0x000CA000UL
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};
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/* IRQ */
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static const hrt_address IRQ_BASE[N_IRQ_ID] = {
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0x00000500UL,
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0x00030A00UL,
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0x0008C000UL,
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0x00090200UL
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};
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/*
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0x00000500UL};
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*/
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/* GDC */
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static const hrt_address GDC_BASE[N_GDC_ID] = {
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0x00050000UL,
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0x00060000UL
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};
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
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static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
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0x00000000UL
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};
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/*
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static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
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0x00000000UL};
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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0x00090000UL};
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*/
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/* GP_DEVICE (single base for all separate GP_REG instances) */
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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0x00000000UL
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};
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/*GP TIMER , all timer registers are inter-twined,
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* so, having multiple base addresses for
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* different timers does not help*/
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static const hrt_address GP_TIMER_BASE =
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(hrt_address)0x00000600UL;
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/* GPIO */
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static const hrt_address GPIO_BASE[N_GPIO_ID] = {
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0x00000400UL
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};
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/* TIMED_CTRL */
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static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
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0x00000100UL
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};
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/* INPUT_FORMATTER */
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static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
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0x00030000UL,
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0x00030200UL,
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0x00030400UL
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};
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/* 0x00030600UL, */ /* memcpy() */
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/* INPUT_SYSTEM */
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static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
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0x00080000UL
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};
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/* 0x00081000UL, */ /* capture A */
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/* 0x00082000UL, */ /* capture B */
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/* 0x00083000UL, */ /* capture C */
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/* 0x00084000UL, */ /* Acquisition */
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/* 0x00085000UL, */ /* DMA */
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/* 0x00089000UL, */ /* ctrl */
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/* 0x0008A000UL, */ /* GP regs */
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/* 0x0008B000UL, */ /* FIFO */
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/* 0x0008C000UL, */ /* IRQ */
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/* RX, the MIPI lane control regs start at offset 0 */
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static const hrt_address RX_BASE[N_RX_ID] = {
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0x00080100UL
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};
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/* IBUF_CTRL, part of the Input System 2401 */
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static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
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0x000C1800UL, /* ibuf controller A */
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0x000C3800UL, /* ibuf controller B */
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0x000C5800UL /* ibuf controller C */
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};
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/* ISYS IRQ Controllers, part of the Input System 2401 */
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static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
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0x000C1400ULL, /* port a */
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0x000C3400ULL, /* port b */
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0x000C5400ULL /* port c */
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};
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/* CSI FE, part of the Input System 2401 */
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static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
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0x000C0400UL, /* csi fe controller A */
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0x000C2400UL, /* csi fe controller B */
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0x000C4400UL /* csi fe controller C */
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};
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/* CSI BE, part of the Input System 2401 */
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static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
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0x000C0800UL, /* csi be controller A */
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0x000C2800UL, /* csi be controller B */
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0x000C4800UL /* csi be controller C */
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};
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/* PIXEL Generator, part of the Input System 2401 */
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static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
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0x000C1000UL, /* pixel gen controller A */
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0x000C3000UL, /* pixel gen controller B */
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0x000C5000UL /* pixel gen controller C */
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};
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/* Stream2MMIO, part of the Input System 2401 */
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static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
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0x000C0C00UL, /* stream2mmio controller A */
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0x000C2C00UL, /* stream2mmio controller B */
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0x000C4C00UL /* stream2mmio controller C */
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};
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#else
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#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
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#endif
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#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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